DK151439B - PROGRAMMING MANAGED DISTRIBUTOR - Google Patents

Description

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χ 151439

BACKGROUND OF THE INVENTION The present invention relates to a program memory controlled transmission system containing functions controlled by a computer for the purpose of performing functions which are of the kind specified in the preamble of claim 1.

5 In the construction of conventional communication stations, ie. by providing telecommunication functions in stations without data processing, it is known to divide the intermediary station into separate function blocks so that each block performs functions that can be easily delimited against functions in other blocks, so that when cooperating between the function blocks the simplest possible boundary sections occur with as few signal lines as possible. Examples of function blocks include subscriber monitoring blocks, selector blocks, blocks for connecting the switching station to various signal systems for interurban connections, blocks for analyzing possible connection paths and for selecting one of the possible connection paths and blocks for charging purposes.

In principle, there are only two function block types.

The first type comprises executive organs, viz. bodies performing direct telecommunications functions, e.g. in accordance with the coordinate principle working voters, and governing bodies governing the executive bodies, e.g. causing potential changes at the coordinate selector's maneuver points. The second function block type comprises exclusively governing bodies which mainly control the cooperation between the function blocks. For example, a marking means which performs the said selection of a possible connection path belongs to this second function block type.

If a computer is added to control such a system, which consists of function blocks of both the aforementioned types, an extension of the system is obtained, by which e.g. from the publication "D-10 Electronic Switching System" in the journal "Japan Telecommunications Review" - Vol. 13, 35 Nos. 3 and 4, and Vol. 14, No. 1, is known to design all of the controlling organs of the original conventional system as parts of the computer. The computer consists of at least one

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2 151439 computer with a control unit and a store for instructions and data, while the functions of the actual system or the state data of the executive organs are stored in the form of instruction columns in the instruction store, or in the form of data groups, so-called variable groups, in the data store, and they are addressed, processed and changed by the controller. The controller contains an arithmetic unit and a number of registers, e.g. information registers and address number registers, for briefly storing instructions, respectively variables and their addresses in the instruction and data warehouse, respectively, which addresses are obtained either as the result of an address calculation by an arithmetic unit or replaced as a directly applicable variable from the stocks. The purpose of the present description is not to explain the working method known per se to a computer, only the addressing methods used in known systems must be explained briefly, since the basic idea of the system according to the invention will appear much more clearly here.

As mentioned above, instruction columns are stored in instruction stores, each consisting of several instructions. Each instruction is assigned a number as an address, and instructions in a column have consecutive, growing address numbers in the calculation method used. In processing a column, it is normal that the first instruction of the column is addressed, read and processed, and that the last step of each instruction causes the associated address number to be increased by one unit in the calculation method used by a "+ l". "addition means, thereby initiating an addressing of the next column-related instruction. In addition to this normal processing, there are so-called 30 hop instructions which, instead of the step involving an address number increment on one unit, specify a whole new address number in the instruction store, to which address number to jump to process it under this hop address number stored information, followed by the instructions if consecutive address numbers are obtained in accordance with the normal calculation.

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3 151439

As mentioned above, so-called variables which store addresses, constants or state information are stored in the data store. While each instruction consists of a constant number of binary bits selected for instruction storage, the variables consist of different numbers of consecutive bits in the data store. In the data store, words, each consisting of a constant number of binary bits selected for data storage, are stored, with an address number associated with each word. There are variables that include 10 parts of a word, a whole word or more than one word, and it is one of the tasks of the controller to process a specific variable. For example, if relates to the state information of mutually similar organs, the organs are defined by consecutive index numbers, and all the variables of the organs are united in the data store to a coherent variable group. In the data store access to a variable for a particular organ can be provided if the address number of the words containing the beginning of the first variable of the group, the constant number of bits that each variable in the group consists of, and the organ index number is known. This prior art data technique for providing access to a variable is explained in connection with an example where it is assumed that the words of the data store each contain 16 bits, that a variable group consisting of 256 variables on every 25 four bits, has the starting address number 3022, and that the variable for the body having the index number 45 among the occurring index numbers 0-255 must be processed. The 4 x 45 = 180 bits that are included in the variables for the organs with the index numbers 0-44 record 11 whole words and 4 'bits of the twelfth word in the 30 variable group (180 = 11 x 16 + 4) and it searched Accordingly, a variable occupies the second quarter of the twelfth word with the address number 3033. The controller contains a conversion means which performs the said one, in order to provide access to a variable # required calculation, 35 but it is not necessary to go into the working method of the to describe the program warehouse's tiered distribution facility.

151439 4

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The address numbers explained above for the addressing of the instructions in the instruction store and the addressing of the words in the data store form part of instructions and variables in the known program storage controlled communication systems, and an intrinsic data processing is obtained, by which the division selected in the conventional system in function blocks completely disappears. Said merging of addresses does not in itself constitute a disadvantage to the system when the data processing has only started correctly, when the computer is working flawlessly and when nothing is changed by the actual system, ie. when the number of executive organs is not changed and when the first appearing organs should never be renewed with replacement with technically superior organs, which are characteristic of 15 other state information and other variable forms. Those skilled in the art summarize the said term and say that the said merger is not disadvantageous as long as no special treatment is required of the intermediary. By "special treatment" is meant here all the working processes required in addition to the normal operating processes, e.g.

by design and construction, by modifications or extensions, or by disruptions in a plant. On the basis of experience, it is already apparent at the commencement whether or not the data processing methods used allow such special processing. After commissioning, the cost of special treatment at known program warehouse managed intermediation systems constitutes an excessive proportion of the total cost of the operational system, and the cost of a system development must also be reduced if these systems must also be reduced if these systems can claim economically compared to conventional plants.

The object of the invention is to provide a plant of the kind mentioned above, which is suitable for special processing of the said kind and in which the division into functional blocks does not disappear, even during the data processing, and in which the said braid for the addresses is avoided. .

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5 151439

This is achieved by a system which according to the invention is peculiar to the design and arrangement specified in the characterizing part of claim 1.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in more detail with reference to the accompanying drawings, in which 1 shows the basic structure of a program controlled transmission system according to the invention; FIG. 2 is a more detailed view of such a plant whose function blocks are associated with spaced apart bearings; and FIG. 3 and 4 plants, in which the said separate stocks are combined into plant stocks.

In FIG. 1, in the proposed transmission system, the system division initially described with the two functional block types is used. In the FBI function block respectively FB3 of the first type are indicated subscriber monitoring circuit LAH, selector step TLN as executive and associated governing body LAS, respectively TLS. By contrast, block FB2 is a function block of the second type and contains a connection path analyzer PA. In FIG.

20 1, the said function blocks FBI, FB2 and FB3 symbolize a conventional transmission station. Together with a computer D, of which in FIG. 1, the controller CPU and two function blocks FB4 and FB5 are indicated, and in which the controlling means LAS, PA and TLS are included, a program controlled 25 transmission system is obtained. In principle, the function blocks FB4 and FB5 do not differ from the function blocks in the actual transmission station, as the function block division described initially can be carried out even in the data processing. Thus, for example, the function block FB4 symbolizes the second function block type, and it comprises an exclusively controlling body JOB with the task of assigning the functions priority grades and thereby determining the order of execution of the functions. The function block FB5 symbolizes the first type, which includes executive organs.

In the computer, such means are e.g. introducing and dispensing means IOQ, as shown in FIG. 1 is indicated by the symbol of a magnetic tape player and its controller

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6 151439 Organ IOS. In order to understand how easily a special treatment of the above kind can be carried out at the proposed plant, it is not necessary to familiarize yourself with the computer. the working method of the plant and the controlled plant to a greater extent than 5 explained above.

If it is possible to maintain the described function block division completely, even in the program storage controlled distribution system, it will be easy to perform the special processing. This is achieved by the fact that each function block 10, regardless of whether it belongs to the actual system or the computer, comprises in principle its own instruction store PS and its own data storage DS with addressing inputs and read and write contacts, respectively. It depends on the type of computer whether a function block's instruction and data warehouses are placed apart or assembled. FIG. 1 shows the latter case, which requires a corresponding number of bits for instructions in the instruction store and for the words in the data store, and in which case the said read or write contacts are connected via a common read or write line, respectively, to an information register IR in the control unit . In the control unit's read and write operations in the instruction and data warehouses, respectively, 25 variables are temporarily registered in the information register. Each function block further comprises an addressing means AD connected to the control unit. It is not possible to activate the addressing inputs of an associated memory by any means other than by means of said addressing means, by means of which addressing signals arriving in the memory are decoded in a known manner in an address decoder ADEC.

It is known in function blocks of the first type to place separate so-called regional computers, which in themselves comprise regional control units, regional instruction stores and regional data stores, and which perform routine functions of a minor nature, e.g. checking checkpoints for the executive organs or reshaping call signals. However, the aforementioned regional control units have an impact

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7 151439 does not cooperate between the function blocks and communicates with the central unit CPU in exactly the same way as the above-mentioned instruction and data stores PS and DS, exclusively via the addressing means AD. In FIG. 1, for the sake of clarity, no regional data is shown.

The cooperation between the controller and the addressing means is shown in FIG. 1 is merely suggested in principle and will be described in more detail below. The basic idea is that each addressing means comprises addressing parameter records 10 APR, in which addressing parameters which are associated with the data structure of the associated function block stores are stored and are required to calculate the addresses of instructions and words. Since the address calculation method is the same for all function blocks, an address calculation unit ACU which includes an selector switch SD, an arithmetic unit ARU, is arranged in the control unit for all the addressing means. the initially mentioned "+ 1" addition means, an address number register AR and the initially mentioned conversion means TD. The function blocks are assigned block number and the selector switch is set by means of a block number which is entered by the control unit in a block number register VNR. Hereby, one of the function blocks is named for a data processing operation. Said block number register is one of a number of operational parameter registers OPR, via which the controller transmits operation parameters to the address calculation unit. The operating parameters specify in a terminology for the functions of the controlled system which of the aforementioned functions are to be performed and thus are not bound to the data structure in the respective block stores. On the basis of the addressing and operation parameters summarized in the addressing unit, this calculates the address number for an instruction or for a word in the called function block repositories. The calculated address number, which applies only to the called function block, is recorded during the operation itself in the said address register and transmitted via the dial switch. to the respective address decoder. The temporal

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8 dependent operations of the operation steps are controlled by the controller in accordance with known computer machine methods which do not need to be explained further herein.

Referring to FIG. 2 and 3, the addressing parameters registered in the addressing parameter registers APR and the CPUs registered by the operating unit CPU via operation parameter registered OPR for the addressing calculation unit ACU transmitted operational parameters are described in detail. Two of the addressing means AD are shown, each comprising a 10 state code register SR, a number of hop registers JR and a number of calculation data registers CDR. The selector switch SD comprises a plurality of selector planes which, in accordance with the above, are set by a block number inscribed in the block number register BNR.

The state of the respective function block is in binary

encoded form registered in the state code register SR, whereby it e.g. is defined that the block is in normal operating condition, that the block's instruction store is being filled with an instruction column, that the block's variable is being updated, or that the block is being checked. A mode selector SSD connects the state code register of the called block to a state table ST in the calculator. The state table determines whether, on the basis of the present block state and partly a control number, an address number 25 must be transferred to the address decoder address decoder ADEC

or not, the table activating or deactivating a port GI. The control unit registers in the auxiliary register AXR belonging to the operational register OPR the said control number, such as the control unit. consists of the calling block's block number. For example, if the subscriber surveillance block FBI of FIG. 1 is in normal operating condition, no access can be formed for the feed block FB5. Since such an attempt to provide access must not occur at a faulty working station, in this case the state table triggers 35 alarms in an alarm unit AA. A more accurate description of the state table is not required to understand the addressing process of the proposed transmission system. The above

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9 151439 for the mentioned address register AR is connected via the gate GI to an address selector ASD whose outputs are connected to the function decoder's address decoder.

In the proposed program storage managed mediation system, a so-called global hop instruction contains the operating parameters that specify to which function block to jump and at which hop position within its instruction column the data processing is to take place. However, as in the known plants, the accumulation position is not expressed by an address number, but by a so-called hop number. By using the head number, the advantage is obtained that in connection with the construction or reconstruction of a function block, but independently of the structure of the instruction column, it is defined that it must be jumped in by an operation determined by an associated head number. Said build-in operation is one of the functions performed by the block and which remains unchanged, although it is e.g. in connection with a reconstruction, a new serial number is assigned to the instruction column of the respective instruction store PS. The controller registers an ordered hop number as one of the above-mentioned operation parameters in a header register belonging to the operation parameter register JNR, the output of which is connected to a header selector JSD, which, like all selectors in the selector switch, is set to the called function block which transfers the header number to a in the addressing means of the called block. The hop count decoder is associated with the said jump register JR such that a read register of the jump register belonging to the transferred hop number is made. In the hop register, 30 serial numbers are registered, each defining for the corresponding instruction column the difference between the address number of the first instruction, the so-called column address number, and the address number of a hop number defined by the hop number. In principle, the read outputs of all hop registers in all addressing means are connected to the arithmetic unit of the address calculator. However, if the column address number of each function block, as assumed in FIG. 2, 10 is "0", the hop registers are directly linked to said address register AR, which also cooperates with a "+1" addition means ADD4. Even without a detailed description of the individual control steps of the control unit, it can be seen that the address register on the basis of a heap number receives and records the address number which after the transfer via the activated gate GI and the address selector to the address decoder for the called function block addresses it to the said heap number related instruction, and that, with a normal continued execution of the instruction column, the registered address-10 number is increased by one serial number unit time after time.

Although so-called local hop instructions are also interrupted the normal execution of an instruction column, but a local hop position must be jumped within the column itself. Although it does not matter in principle whether it is a local or a global hop instruction, in the definition of a hop position, the benefit obtained and mentioned above by hops, however, comes mainly to its right in the global case. The possibility of carrying out the above-mentioned special treatment of the mediation plant is not affected by the local hop instructions, and therefore no head numbers associated with the local hop positions are required. In order to avoid an excessive number of hop-25 registers, it is often more convenient, in accordance with the introductory description, to define the local hop-in positions by means of address numbers which the controller directly transfers to the address number register.

At the proposed dissemination system, an instruction for a read and write operation in one of the data layers DS contains, in addition to the current block number, operation parameters which indicate the ordered variable type and, for a variable group, the index number of the organ to be processed. However, the variable type is not, as is the case in known plants, and as is initially explained, is determined by the address number of the word containing the beginning of the variable group, but by a so-called variable number. By using variable numbers, the advantage is obtained that read and write instructions remain unchanged, even though the division into storage fields for the occurring variables and the variable groups in the called data store is changed.

5 Such a divisional change is imposed e.g. of additional means in connection with an extension of the station or more modern means whose state variables relative to the variables of the previously used means consist of a different number of bits. The controller registers an ordered variable number as one of the operation parameters mentioned above in a variable number register VNR associated with the output register whose output is associated with a variable number selector VSD which is set on the called function block which transfers the variable number to a variable number decoder. VDEC in the addressing means of the called block. The variable number decoder is associated with the above-mentioned computation address records CDR such that a reading of the computational data register belonging to the transmitted variable number is recorded and which, in accordance with the introductory description, has registered the address number of the data storage word containing the beginning of the variable group defined by the respective variable number and the number of bits each variable in that group consists of. The contents of the computational data register to which access is formed and the contents of an organ index register DIR are transferred to the initially mentioned conversion means. TD, which in a known manner carries the address register of the word to be read or written respectively. and defines the bit variable of the respective variable in the information register IR 30 content. In this connection, it is not necessary to go into detail in known computer technology, and in fig. 2 and 3, the bit position determination is merely indicated by a dotted line of function from the converter to the information register.

It is already apparent from the foregoing description that the function block division is not abolished due to the data processing, since the controller basically has access only to the instructions and to the variables belonging to the function block.

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12 151439 block whose register number is registered in the block number register. Accordingly, each of the function blocks in the proposed transmission system, e.g. in connection with the design, with a replacement due to a fault or 5 with a reconstruction is treated entirely for itself provided that the respective operating state is registered in the corresponding state register. The possibility of carrying out the above-mentioned special treatment of the proposed plant is more clearly explained in connection 10 with further examples at the end of the description.

While using existing computer technology is more economical to use a few large stocks rather than many small stores, it is not necessary for this reason to forego the advantages described above for a complete functional block orientation. It is assumed that all storage blocks of function blocks must consist of storage fields in a system's instruction store SPS and a system's data storage SDS, and that the storage facilities of said plant are arranged in one in FIG. 3, the addressing inputs of the repositories are connected to a common repository address decoder SADEC, while the read and write contacts of the repositories are connected via a common line to the information register IR in the CPU unit. In this way, in connection with FIG. 2, which results in a single address signal line from the output of port GI to the input address decoder input.

The summary of the function blocks instruction columns in the system instruction store requires that each addressing means AD, of which in FIG. 3, two, 30 are shown in a first embodiment comprising a column address register belonging to the address parameter register CAR, in which the column address number of the function block is stored. The column address register of the addressing means is associated with a column selector CSD which, when set to one of the block numbers, transfers the respective column address number to a first addition input of an addition circuit ADD1 included in the arithmetic unit

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13 151439 ARU and whose sum output is associated with the address number register AR. The "+1" addition means ADD4 repeatedly mentioned, or said jump register JR's read lines, respectively, are connected to the addition circuit ADD1's second and third addition inputs respectively. In addition to those shown in FIG. 2 described steps are added in this way, e.g. in the execution of a hop instruction, the column address number for one of the serial numbers.

In another embodiment not shown in FIG. 3, instead of the serial numbers belonging to the hop-in positions defined by the hop numbers, the corresponding address number of the system instruction store is stored in the hop register, which is transferred directly to the address number register of the control unit. Said second embodiment thus requires neither the column address register CAR nor the column selector CSD and the addition circuit ADDI, and it therefore seems to work more simply than the one shown in FIG. 3. However, an important advantage of the first embodiment is that in connection with a repositioning of the facility instruction store, in which the instruction columns whose internal structure does not change are moved to new storage areas, only a change of column address numbers is required, while the second embodiment requires , that all hop registers are re-filled.

25 Since it is not necessary, but on the contrary, for an optimal utilization of the system data warehouse to store all variable groups for one function block one after the other, the summary of all variable groups for all function blocks in the system data database simply requires that in the calculation data register of the addressing body CDR 30 corresponding address numbers of the plant data SDS are recorded for the variable addresses start addresses. This leads to a data addressing comparable to the said second embodiment of the instructional addressing.

35 Regarding both the data addressing and the instructional addressing, the location of the instruction columns and variable groups in the repositories has not changed anything about it.

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14 151439 proposed system principle, which consists of each of the function blocks having storage, to which access can only be created by the associated addressing means.

5 In FIG. 4, there is shown an association of the addressing means of all the function blocks, the registering means mentioned above being included in three storage fields for the addressing means SAD of a system. The first storage field SF1, addressed by a block number decoder 10 BDEC, stores for each function block an addressing word composed of the following basic address numbers JBA and CBA for the second and third storage fields, of said state code and of the said column address number,

The second storage field SF2, which is addressed by means of a call-by-number decoder SJDEC, comprises the above-described hop registers JR in all addressing means, in that a function block belonging to a function block registers a group with consecutive address numbers, one number for each heap number, where the address number belonging to the first 20 heap number in a group forms one of the base address numbers for the second storage field, which heap base address number JBA belongs to the respective function block's address word in the first storage field. The third storage field SF3, addressed by one of the plant variable number decoders SVDEC,

25 comprises the computational data areas described above CDR

for all the addressing means, in that a computational data register belonging to a function block forms a group of consecutive address numbers, one number for each variable number, the address number being; belonging to the first 30 variable number in a group, forms one of the base address numbers for the third storage field, which calculation database address address number CBA belongs to the respective function block's address word in the first storage field.

In the address calculation unit ACU of a switching system provided with the addressing means SAD 35, the selector switch described above is superfluous, since the block number register BNR directly feeds the block number decoder.

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The BDEC for the first storage field, and because the state code or the column address number contained in the addressing word to which access is thus created, is transmitted directly to the state table ST, respectively to the ADDI addition circuit. The base address number, or the computational data base address number, respectively, in the addressing word to which access is formed is transferred to an additional circuit ADD2 or ADD3 in the arithmetic unit ARU, respectively. The other addition inputs for the said additional circuits ADD2 and ADD3, respectively, are connected to the hop count register JNR, respectively to the variable number register VNR, and their sum outputs are connected to the plant call decoder SJDEC, respectively to the plant variable number decoder SVDEC.

15 To better explain the addressing step, FIG. 4, a decimal number example is introduced and it is assumed that the function block with block number 55 is jumped at the jump-in position with the jump number 2. On the basis of this jump instruction, the controller registers in the block number register the number 55 and in the jump register the number 2.

The block number decoder activates addressing input # 55 for the first field SF1 of the system addressing means SAD, and the associated addressing word is read. It is assumed that said addressing word contains 320 for the computational data base address number, 750 for the base address number, and 460 for the column address number, and that the state code activates the port GI. In the addition circuit ADD2, the sum 750 + 2 = 752 is generated by the base address number and the hop number, which sum is transferred to the plant count decoder SJDEC, 30 whereby in the second storage field SF2 access to the hop register with address number 752. It is assumed that the hop register group for the function block with the block number 55 consists of four hop registers with the address numbers 750-753.

In connection with FIG. 2, it is disclosed that serial numbers are stored in the hop registers, the serial number O defining the beginning of an instruction column with an associated number of numbers O. This means that during each jump 16

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base address number, e.g. below the address number 750 for the block number 55, the number 0 is registered as the serial number. Further, it is assumed that in the hop register with address number 752, the number 25 is registered as the serial number, which number of the addition circuit ADDI adds to the column address number 460. This results in the instruction column of the function block with block number 55 in the system instruction store beginning under the address number 450. and that the pick-up position with the hop number 2 has the address number 10 460 + 25 = 485.

Furthermore, it is assumed that the said instruction with the address number 485 contains the order in order to read the variables in the variable group with the variable number 1 in the function block itself with the block number 15 55, and that the means with the index number 45 stands in turn. The control unit registers the variable number 1 in the variable number register VNR and the index number 45 in an organ index register DIR associated with the conversion means TD. The ADD3 addition circuit generates the base address number and calculation data ..... the variable number sum 320 + 1 = 321, which is transferred to the system variable number decoder, whereby in the third storage field SF3 access to the calculation data register with the address number 321. It is assumed that the calculation data register group for the function block with block number 55, 25 consists of three registers with corresponding address numbers 320-322, the variable number 0 being also used to define one of the three occurring variable groups. Finally, it is assumed that in the calculation data register CDR with the address number 321 to which access is created, as the starting address 30 of the ordered variable group, the number 3022 is stored in the system data store and the number 4 as constant, indicating the number of bits per unit. variable. The conversion element TD initially referred to in the address calculation unit ACU assesses the transmitted calculation data and the body index 35 and calculates that in the system data store, as explained earlier, the second word quarter in the word with the address number 3033 must be read.

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17 151439

Although the proposed addressing steps are described with reference to the aforementioned three storage fields for the system addressing means and the three independently operating addition circuits, it will not present difficulties for those skilled in the computer engineering to adapt the said steps to the operation of the applied control unit. For example, if If additional registers and ports are used, a single addition circuit can be satisfied, or it is possible to merge the said three decoders for the plant addressing means SAD into a single decoder. In addition, it is one of the tasks of the control unit to temporarily separate the access to the instruction store from the accesses in the data store and to manage e.g. The use of the "+1" additive ABD4. In the present description, it is not necessary to go into the computer technique known per se, as in FIG. 2-4 are merely indicated by three ports G2, G3 and G4 which control the inputs to address the number register AR and the use of the "+1" addition means ADD4.

In FIG. 2-4, the registers of the addressing means, or the storage fields of the addressing means of the addressing device, are connected only through reading cables to the control unit, and the process of addressing the instructions and variables of a function block is described on the condition that the base addresses, serial numbers, calculation data etc. are already registered in registers arranged for this purpose. , and storage fields, respectively. At least at the start-up of the transmission system, but also at extensions, improvements and the correction of errors, the addressing means must be fulfilled. Therefore, it is convenient to arrange the addressing means into a function block of the second type, this addressing function block being associated with a corresponding addressing instruction column in the system instruction store, where the addressing function block variable groups of the addressing function block form. By means of the instruction column of the addressing block, in addition to the addressing characters described, e.g. also, in what way

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18 151439, by means of the filling means and on the basis of an examination of unused areas in the computer's storage, variables for the system addressing means are provided and inscribed.

In an example to illustrate how easy it is to carry out the aforementioned special treatment of the proposed mediation system, it is assumed that for one of the function blocks an improved instructional column must be introduced, which measure by known even interlaced plants necessitate a reorganization of the stocks, ie. a fundamental refill and a new control of all instructional columns and a complete system shutdown. At the proposed plant, the new instruction column is introduced into a reserve function block with a reserve block number. The filling, updating and checking of the reserve block, respectively, takes place in time sections which, in accordance with the rules known per se for different priority grades, are determined for such special functions so that there is no disruption to the normal work that continues with the original function block until the spare block is ready to take over the job. The block replacement also occurs without interfering with normal work, the block replacement being that the original block is assigned a waiting state and that the reserve block is assigned to the normal operating state, while a block number converter BNCT with which block number register BNR as indicated in FIG. 4 is connected, the original block's block number converts to the spare block number. If the new block still does not work flawlessly at the normal working 30, then just a return to the old block will occur. When, after a trial period, it has become apparent that the old block is no longer needed, its original addressing word is replaced with the backup block's addressing word. Hereby, the reserve block 35 is automatically assigned the original block number so that said block converter is released and the reserve block number is again available for the next special processing. A complete stand-

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19 151439 A complete refilling of the warehouses or any other interruption of operation does not occur by special treatment of the proposed plant.

It will be readily appreciated that the above-described interference-free transition from an old to a new function block is of great importance for a switching station which, for reasons of operational security, uses two parallel operating computers in known manner. In prior art systems, the said reorganization of one computer's storage system makes it impossible to cooperate in parallel with the yet unorganized second computer, because each operation step of one computer must be compared with the corresponding step of the other computer. Only when both computers are reorganized, which is associated with a renewed start-up, at which all existing connections break down, the desired operational reliability in parallel operation is again provided.

If two systems of the present invention operate in parallel and an error occurs, the troubleshooting is already facilitated by the function block just called in the case of alarms being always registered in the block number register.

When it is known in a manner known per se for which computer the said block is faulty, the faultless block is connected to both the computers. This means that operating security is almost 10.0% restored. Then the faulty block as described above is replaced and finally the complete cooperation is resumed. A fresh start of telecommunications does not occur at all in the correction of an error.

If an improved instructional column is to be introduced into the proposed transmission system by two parallel operating computers, the columns of both computers as described above are replaced using reserve block numbers, the said steps of switching being performed completely parallel to the two computers. No disruption is caused by this change and reliability is not diminished during such special treatment.

Claims (8)

0 20 151439 Patent Claims. A program storage controlled intermediary system for performing functions comprising means controlled by a computer, which system for performing various organ and computer functions partly comprises function blocks (FBI, FB3, FB5) of a first type, of which each block performs functions bounded by the functions of the other blocks, of which each block contains executive organs as well as controlling organs required for executive control, and partly function blocks (FB2, FB4) of a different type, of which each block contains only control means (PA, JOB) which perform control functions in which the controlling means for both function block types are included in the computer, which for the implementation of the system control comprises at least one control unit ^ (CPU) connected to the control means for said function blocks, characterized in that: (a) each of said function blocks (FBI, FB2, FB3, FB4, FB5) is defined by an associated function block number; b) that in each function block for storing the control information of the respective controlling bodies, an instruction store (PS) and a data store (DS) are provided, whose addressing inputs over an address decoder (ADEC) are associated with one belonging only to the respective function block. addressing means (AD) with associated storage, and c) a selector switch (SD) exists which is set by means of one of said function block numbers such that the addressing means (AD) of the defined function block is connected to the controller (CPU). , OV / which, in turn, by means of the information stored in the addressing means (AD), controls the writing or reading in the said instruction and data stores respectively, the information contained in the addressing means (AD) indicating the relationship between the addressing addresses (AD) and the instruction store (PS) as well as the addresses of the data warehouse (DS). System according to claim 1, characterized in that: (a) each addressing means (AD) contains a state code register (SR) in which the operating state of the associated function block is stored in coded form and which state code register is associated with a state selector (SSD) ) for the selector switch (SD), and b) the controller (CPD) contains state monitoring means (ST, AXR, Gi) which, depending on the state code received via the mode selector, monitors said writing or reads in the function block memory (PS, DS), (Fig. 2). Installation according to claim 1, characterized in that: (a) each addressing means (AD) contains addressing parameter registers (APRs) in which addressing parameters are defined which define the storage structure of the control information in the storage of the corresponding function block; (CPU) there is a common address calculation unit (ACU) for all 20 addressing bodies and associated operational parameter registers (OPRs), to which belongs a block number register (BNR) and in which for carrying out a control operation such parameters which are not bound to and (c) the address calculation unit (ACU) comprises an arithmetic unit (ARU) and is arranged to record in an address number register (AR) an address number calculated on the basis of the addressing and operation parameters which is transferred to the associated stored (PS, DS) address decoders (ADEC) via an address selector (AS) set on the respective function block D) in selector switch (SD) f (fig. 2). System according to claim 3, characterized in, 55 a) that the addressing parameter register (APR) in each of the addressing means (AD) contains a plurality of calculation data registers (CDRs) to which access can be generated by a variable number decoder (VDEC) , and each of which is defined by its respective variable number, which registers are arranged to record calculation data containing a digit constant indicating how many consecutive bits in the data store (DS) each of a number of the said variable number defined variables consist which variables are included in the control information for the respective function 2q block and sequentially form a variable group, the beginning of which is included in a data storage word whose address number also belongs to said calculation data, b) the device is such that the said calculation data is transferred to a conversion device (TD) located in the address calculation unit (ACU) to be converted here so that the address number register (AR) is transferred to the address number under which data stored in the data store (DS) can be accessed by a variable ordered by the controller 20 (CPU) in the said variable group, and c) the operation parameter registers (OPR) contain a variable number register (VNR). for registering variable numbers which, via a variable number selector (VSD) in the selector switch (SD), is fed to one of the said variable number decoders (VDEC), (fig. 2). System according to claim 3, characterized in that: (a) the address parameter registers (APR) in each of the addressing means (AD) contain a column address register (CAR) in which a column address number is registered and a number of hop registers (JR) to which can be accessed by means of a hop decoder (JDEC) and in which are registered serial numbers, by which the column address number is accessed at the beginning of an instructional column, to which access can be made by successive 23 1 5 1 43 9 o address numbers of the instruction store / and which are included in the control information for the respective function block, while each of the serial numbers indicates the difference between the column address number and the address number of an instruction defined by a 5 of a number of heap number instruction in said instruction column; b) the operation parameter registers (OPR) contains a hop register (JNR) for recording the said head numbers, which in each addressing body defines every 20 set of hop registers and which is passed via a hops number selector (JSD) for the selector switch (SD) to one of the said hop number decoders (JDEC), and c) a column column (CSD) associated with the selector switch (CAR) associated with the addressing bodies (CAR). is connected to a first input of a first addition circuit (ADDI) of the arithmetic unit (ARU), with the second input of the hop registers (JR) for all addressing means and whose sum output is associated with the address number register (AR), (Fig. 3). System according to any one of claims 3-5, characterized in that said control unit (CPU) controlled by separate address decoders (ADEC) provide instruction and data stores (PS, DS) and said address selectors (AD) is made up of storage fields in a plant's instruction store (SPS) and in a plant's data warehouse (SDS), which is provided with at least one plant address decoder (SADEC) associated with the address number register (AR), where one of the variable groups is stored in each storage field. , or instructional column, respectively, of which a function block's control information consists. Installation according to claims 2 and 6, characterized in that: (a) said state registers and addressing parameter registers for all the addressing means are 35 storage fields (SF1, SF2, SF3) in a plant addressing device (SAD), b) said selector switch is constituted by a block number decoder (BDEC); (c) the said head number decoders, or variable number decoders, respectively, for all the addressing means are constituted by a plant head number decoder (SJDEC) or a system 5 variable number decoder (SVDEC), respectively, which are decoded into the said storage fields (SF1, SF2, SF3) to access address words and the mentioned sequence numbers for the jump registers (JR), respectively, the said calculation data for the calculation data registers (CDR), while each addressing word to which access is generated by means of one of the block numbers, in addition to said state code and said column address number, contains a background address number (JVA) associated with it in the heap number decoder (SJDEC) This storage field (SF2) for the instruction column of the respective function block provides access to the serial number defined by the header number "O" and a calculation data base address number (CBA) which forms in the storage field (SF3) associated with the system variable number decoder (SF3) access to the respective function-20 block calculation data for the variable group defined by the variable number "0"; addition circuit (ADD2), whose signal output is associated with said plant count encoder (SJDEC), and d) the device is such that the variable number recorded in the variable number register (VNR) and said calculation database address number (CBA) is fed to a third addition circuit. (ADD3), the sum output of which is associated with said plant variable number decoder (SVDEC), (fig. 4). System according to claim 7, characterized in that the system addressing means (SAD) is designed so that its storage fields (SF1, SF2, SF3) are arranged as storage fields of the system instruction and system data storage 151439 0 (SPS, SDS) respectively. the said address words, serial numbers and calculation data are accessed by means of the plant address decoder (SADEC).