GB2030333A

GB2030333A - Part-word Addressing

Info

Publication number: GB2030333A
Application number: GB7927417A
Authority: GB
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1978-08-30
Filing date: 1979-08-07
Publication date: 1980-04-02
Also published as: DE2837709A1; DE2837709C2; FR2435088A1

Abstract

A CPU accesses a memory DS with a fixed word length organisation through a set of control circuits SB1, SB2, SB3, SB4 each dealing with access to the memory DS in respect of a "sub-word" consisting of a sub- multiple of the word length. Each control circuit has a device PS for producing a parity bit for the sub-word which it handles, with parity checking used in both directions between the control circuits, which are fed from and controlled by the CPU, and the memory DS. The arrangement is described in connection with a computer controlled telephone exchange using a 16-bit memory in which 4-bit dialled digits and 16-bit addresses are stored. <IMAGE>

Description

SPECIFICATION Part-word Addressing This invention relates to a circuit arrangement for processing subdivisions of words in computer systems and particularly in microcomputer controls for telecommunication switching systems of the type having a central processing unit, a data memory having a fixed-word-length organization connected to the central processing unit via data lines, and a memory control causing data of variable length to be written into and read from the data memory.

In today's electronic telephone switching systems the control is advantageously modular in construction and may be organized in different hierarchical levels: thus the decentralized level is composed of individual modules and so can be expanded as required. The individual modules are controlled by microprocessors, i.e., they form microcomputer systems. Frequently the central level is also controlled by microprocessors. While the memories of the control computer systems are usually organized in fixed word lengths, i.e., the number of locations or bits that can be obtained with a single access has a predetermined value, the data to be processed may have variable lengths for various reasons.A circuit arrangement of the above kind is known in which telephone traffic is controlled by a processor (German Offenlegungsschrift 2,721,235) which has to process, for example, both 1 6-bit addresses and dialled digits consisting of only 4 bits, the individual areas of the data memory having a word length of 6 bits.

Different word lengths may also occur if the computer control is byte-oriented, i.e., processes the information in a word length of 8 bits, while the computer is programmed in a higher-level programming language with a data format of, say, 32 bits. In this case, it is frequently necessary to alter only one byte within a 32-bit word.

In the aforementioned arrangement, a (4-bit) subdivision of a word is written into a desired portion of a memory location (which can hold 16 bits) by being first shifted by a so-called expansion unit or a concentration unit controlled via a check unit and a control unit. To do this, a complete data word containing the subdivision to be altered must be read from a main memory and transferred, e.g. via the concentration unit and an arithmetic unit, to the input of thaexpansion unit.

The expansion unit provides a 16-bit word three subdivisions of which are unchanged, while the fourth corresponds to the new subdivision to be written into the memory. The outputs of the control unit provide write pulses which enable the subdivisions of the word to be written both into portions of the main memory or of a buffer memory into portions of the locations of the data memory.

Thus, the known way of processing subdivisions of a word is quite complex, and needs a considerable amount of circuitry. The concentration unit and the expansion unit contain, besides many other components, ten multiplexers. Furthermore, there is no possibility of checking the subdivisions of the words for errors.

An object of the invention is to provide a fast and reliable circuit arrangement for processing subdivisions of words in computer systems which requires as little circuitry as possible.

According to the invention, there is provided a circuit arrangement for processing subdivisions of words in computer systems including a central processing unit, a data memory having a fixedword-length organization and connected to the central unit via data lines, and a memory control causing data of variable length to be written into and read from the data memory, wherein the memory control contains a plurality of control blocks which can be individually activated by the central processing unit and each of which is assigned to a group of data lines usable for transferring a subdivision of a word, and wherein each of the control blocks is connected to the data memory via an additional data line over which a parity bit generated separately for the respective subdivision of a word can be transferred.

The principal advantage of the invention is that the parity bit formed for each subdivision of a word and written into the data memory together with that subdivision can be checked when the latter is being read out, so that error checking is performed on the individual subdivisions of a word. This results in a considerable improvement in the reliability of the entire computer system.

An embodiment of the invention will now be explained with reference to the accompanying drawing.

The arrangement shown in the drawing forms part of a computer system, and includes a central processing unit CPU which, according to the complexity of the system to the controlled, may be formed from one or more microprocessors connected together by 8-bit data buses. The processing unit CPU has a data output DA, a data input DE, a control output SA, and an address output AA. It is connected to a data memory DS by data buses DLG and DLK, and to the data memory and a memory control SST by an address bus AL and a control bus STL, respectively. In the embodiment shown, the data buses DLG and DLK each consists of 32 wires, i.e., they allow a 32-bit word to be transferred in parallel, while the addres bus AL and the control bus STL consists of fifteen and three wires, respectively.

The unit CPU is connected to a programme memory (not shown) by an, e.g., 8-wire, instruction bus IL and receives from this memory the instructions to be executed.

The memory control Sst contains four memory blocks SB1 to SB4, which are so inserted in the data buses DLG and DLK that each of them is assigned to a group of eight outgoing and eight incoming wires. The individual control blocks SB1 to SB4 are activated by control signals from the central processing unit; in the active state, they enable the respective associated eight incoming or outgoing data wires, so that a subdivision of a word can be written into or read from the portion of that row of the data memory DS which has been addressed via the address bus AL.

Each of the control blocks SB1 to SB4 also contains a check circuit PS, which forms a parity bit for each subdivision of a word to be written into the data memory DS, and writes this parity bit into the memory together with this subdivision of the word. To this end, one additional single wire is provided between each control block and the data memory DS in either direction, i.e., each memory block SB1 to SB4 is connected to the data memory DS by two 9-wire buses (one per direction). When a subdivision of a word is read from the data memory, the check circuit forms the parity bit again and compares it with the parity bit read from the memory. Thus, data protection is provided for subdivisions of a word, not for complete words as in conventional arrangements.

With the control blocks of the memory control SST, which can be activated on an individual basis, subdivisions of a word~1 byte in the embodiment described-can be written into and read from the data memory DS and, thus, can be altered without first having to perform a read cycle in order to read the whole 32-bit word from the data memory. A memory control SST consisting of four control blocks thus permits byteoriented and parity-protected access to a 32bit data memory.

If the operation code specifies an access to a 32-bit word, all four memory blocks will be activated at the same time. Thus, a byte-oriented organization of the data memory access is also advantageous in that the circuit boards carrying the memory elements have only a limited number of plug connections. In an electronic PABX control constructed in accordance with the invention, the wiring between the memory control and the data memory permits up to eight 32-kilobyte memory boards to be connected to the memory control.

With four such memory controls, a maximum memory capacity of one megabyte (=8x32 kx4) can thus be realized.

In addition, the memory boards can be arranged in the computer system in an advantageous manner. As the boards are distributed around the central processing unit at equal distances therefrom, line lengths and, hence, access times to the memory boards can be kept short.

Claims

1. A circuit arrangement for processing subdivisions of words in computer systems including a central processing unit, a data memory having a fixed-word-length organization and connected to the central unit via data lines, and a memory control causing data of variable length to be written into and read from the data memory, wherein the memory control contains a plurality of control blocks which can be individually activated by the central processing unit and each of which is assigned to a group of data lines usable for transferring a subdivision of a word, and wherein each of the control blocks is connected to the data memory via an additional data line over which a parity bit generated separately for the respective subdivision of a word can be transferred.

2. An arrangement as claimed in claim 1, wherein the data lines are combined in groups each carrying one byte, and wherein the data memory has for each byte of a data word an additional location for storing the parity bit.

3. An arrangement as claimed in claim 1 or 2, and wherein the control blocks include parity-bitcalculating and -comparing check circuits.

4. A circuit arrangement for processing subdivision of a memory word length, substantially as described with reference to the accompanying drawing.

5. An automatic telecommunication exchange in which a circuit arrangement as claimed in any one of the claims 1 to 4 is used.