JP2550537B2 - Time division multiple timer method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a time division multiplex timer system, and more particularly to “1”,
The present invention relates to a time division multiplex timer system of a microprocessor for monitoring a time elapsed from a change point of each of n input signals represented by "0".

2. Description of the Related Art Conventionally, in this type of microprocessor 36, as shown in FIG. 2, the time elapsed from the change points of n input signals S1 to Sn represented by "1" and "0" is monitored. In this case, the timer circuits T1 to Tn are individually required for each of the n input signals.

In such a conventional microprocessor 36,
When the time elapsed from the change point of the input signals S1 to Sn represented by "1" and "0" is monitored, each of the n input signals requires the respective timer circuits T1 to Tn. There is a drawback that the number of timer circuits T1 to Tn proportional to the number of Sn and the mounting area proportional to the number of timer circuits T1 to Tn are required.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional ones. The number and mounting area of timer circuits used for monitoring the elapsed time from the change point of each input signal to the next change point. It is an object of the present invention to provide a time division multiplex timer system capable of reducing and.

Configuration of the Invention A time division multiplex timer system according to the present invention is a time division multiplex timer system of a microprocessor for monitoring the elapsed time from the change point of each of a plurality of input signals, and an individual signal assigned to each of the input signals. A first memory having an address and a change in the input signal from the change point to the next change point of each of the input signals are monitored at predetermined time intervals, and the change point is changed to the next change point. Means for storing the number of times of monitoring up to the first memory in an address corresponding to the corresponding input signal, a second memory in which the same data is stored in the same address as the first memory, and Two
And means for controlling reading of the memory.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to the figure, a time division multiplex timer circuit according to an embodiment of the present invention includes an address generator 1, a calculator 2, and a read unit 3.
It is composed of

The address generator 1 is composed of an address generator circuit 11,
The calculation unit 2 includes a memory 21 and a binary number addition circuit 22, and the reading unit 3 includes a memory 31 and a line select circuit 32 to.
34, a line select control circuit 35, and a microprocessor 36.

The address generation circuit 11 outputs the address assigned to each input signal to the memory 21 and the line select circuit 32 through the bus line 10 in a predetermined time period in a time division manner, and at the same time, outputs this address. Each time, a read / write signal for the memory 21 is output to the memory 21 and the line select circuit 33 via the signal lines 70 and 71.

When a read signal is input to the memory 21 via the signal line 70, the data held in the memory location specified by the address output together with the read signal is added to the binary number via the bus line 20. It is output to the circuit 22 and the line select circuit 34. The data held in the memory 21 is the result of addition of binary numbers processed by the binary number addition circuit 22 when the same address as the address output together with the read signal was previously designated.

The binary number addition circuit 22 adds 1 to the input data, that is, the result of the previous binary number addition, and outputs it to the memory 21 via the bus line 20. Signal line 71 in memory 21
When a write signal is input via the
Write the addition result of this time from to that address.

The operation of reading data from the memory 21, adding 1 to the data, and writing the addition result to the memory 21 is sequentially performed for each address.

When the addition result is not read by the microprocessor 36, a signal for controlling the line select circuits 32 to 34 is sent from the line select control circuit 35 through the signal line 76, and the line select circuit 32 causes the bus line. Ten
Are selected, and the signal lines 70, 7 are selected in the line select circuit 33.
1 is selected, and the bus line 20 is selected by the line select circuit 34. Therefore, the address output from the address generation circuit 11 is output to the bus line 50, the read / write signal output from the address generation circuit 11 is output to the signal lines 74 and 75, and the binary addition is performed to the bus line 60. The binary addition results output from the circuit 22 are output, and these are input to the memory 31. However, in this case, the bus line 50 is unidirectional from the bus line 20.

With the above settings, the memory 21 and the memory 31 have the same condition at the time of writing, so that the addition result added by the binary number addition circuit 22 is written to the memory 21 and at the same time, the same is written to the memory 31. Be seen.

When the addition result is read by the microprocessor 36, the addition result read signal is sent to the signal line 77 by the microprocessor 36, and the line select control circuit
A signal for controlling the line select circuits 32-34 is sent from 35 through the signal line 76, the bus line 30 is selected in the line select circuit 32, the signal lines 72, 73 are selected in the line select circuit 33, and the line select In the circuit 34, the bus line 40 is selected. Therefore the bus line
An address bus, a read / write signal, and a data bus from the microprocessor 36 are sent to 50, the signal lines 74 and 75, and the bus line 60, respectively.

With the above settings, the microprocessor 36 to the memory 31
Can be directly controlled, by giving an address similar to the address individually assigned to each input signal generated by the address generation circuit 11 by the microprocessor 36, the contents of the memory 31 corresponding to any address, That is, the elapsed time from the change point of the input signal is calculated in parallel 2
It can be read by the microprocessor 36 as the progress of the addition process of the base.

The bit numbers of the bus line 20 and the bus lines 40 and 60 are all equal and depend on the number of processing bits of the microprocessor 36. Among the number of bits, the least significant 1 bit is a control bit for starting and stopping the addition processing of binary numbers, that is,
It is used as a bit indicating the change point of the input signal described above, and binary addition is performed with the remaining upper bits.

When the memory 21 and the memory 31 are set to the same condition for writing, only the least significant bit of the bus line 60 is independently controlled by the line select circuit 34, and the read signal is output from the address generating circuit 11 via the signal line 70. Is output,
The least significant bit of the bus line 60 is input to the binary adder circuit 22. The binary adder circuit 22 detects the state of the least significant bit and determines whether to start or stop the addition.

When the binary number addition circuit 22 determines to start addition, the binary number addition circuit 22 performs addition, and the addition result is written in the memories 21 and 31.

Further, when all the addition results performed by the binary number addition circuit 22 are "1", that is, when the count-up is performed, all the bits including the control bits are automatically cleared and the counting is stopped. When the addition cancellation information is sent to the least significant bit, the binary addition circuit 22 judges that the addition is canceled and the control bits are included even if the addition results are not all "1", that is, not counted up. Clear all bits and stop counting.

The least significant bit of the bus line 60 used in the above operation is written in the memory 31 via the bus line 40 under the condition that the memory 31 can be directly controlled by the microprocessor 36.

By the above operation, the elapsed time from the change point of an arbitrary input signal to the next change point can be read out as a result of addition of binary numbers. That is, the elapsed time can be represented by multiplying the result of addition of the binary numbers by a fixed period in which the same address is output by the address generation circuit 11.

As described above, the addresses in the memories 21 and 31 are assigned to the respective input signals, and the elapsed time from the change point of each input signal to the next change point is monitored at predetermined time intervals, and the number of times of monitoring is changed. By storing at the address in the memory assigned to the input signal, the number of timer circuits used for monitoring the elapsed time from the change point of each input signal to the next change point can be reduced, The mounting area of the timer circuit can be reduced by the number of the timer circuits.

As described above, according to the present invention, an address in the memory is assigned to each input signal, and the elapsed time from the change point of each input signal to the next change point is monitored at every predetermined constant time. However, by storing the number of times of monitoring at the address in the memory assigned to each of the input signals, the timer circuit used for monitoring the elapsed time from the changing point of each input signal to the next changing point is stored. There is an effect that the number and the mounting area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. Description of main part code 11 …… Address circuit 21,31 …… Memory 22 …… Binary number addition circuit 36 …… Microprocessor

Claims (1)

(57) [Claims] 1. A time division multiplex timer system of a microprocessor for monitoring an elapsed time from a change point of each of a plurality of input signals, comprising a first memory having an individual address given to each of the input signals. Changing the input signal from the change point of each of the input signals to the next change point at predetermined time intervals, and monitoring the number of times from the change point to the next change point by the first Means for storing at an address corresponding to the input signal in the memory of
Time-division multiplex timer system characterized by including a second memory in which the same data is stored at the same address as the above memory and a means for controlling the reading of the second memory.