JPS62224841A - Operation history storage system - Google Patents

Abstract

PURPOSE:To flexibly select trace data by generating a selection signal required for selecting trace data with the aid of an output signal obtained by masking a signal decided by mask information among plural signals generated corresponding to an operation situation in an information processor. CONSTITUTION:A tracer memory 1 writes and stores the output of a trace data selection circuit 2 and that of a trace data selection code generator circuit 8 at an address specified by an address specifying circuit 3 when a write control part 4 issues a write indication. When the memory 1 in write stoppage receives a read address specified by a diagnosis control part 7 through the circuit 3, contents at the address are read out. Masking any one of control signals S0-S6 based on the mask information of a mask register 10 occurs when the preferential order of the signals S0-S6 is ignored and trace data corresponding to a control signal bit with low priority is selected. Thus trace data can be flexibly modified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation history storage method in an information processing device, and more particularly to a selective storage method for history data.

Prior Art In recent years, information processing devices have become larger and machine cycles have become smaller in order to improve performance. This has made it difficult to control the devices within a single control section, and control sections have become increasingly decentralized. I'm here. Along with this, data to be traced is also distributed among multiple units including each control section, and the amount of data tends to increase. In contrast, tracing data is stored] - Since racer memory is expensive, there is a tendency not to increase its use in hardware. For example, a method of selecting and writing data to be written in advance is adopted.

In FIG. 2, the tracer memory 1 can store the output of the trace data selection circuit 2 at the address designated by the address designation circuit 3 at write/υ when the write control unit 4 issues a write instruction. Further, when the read address designated by the diagnostic control unit 7 is received via the address designation circuit 3 when writing is in a stopped state, it is possible to read the contents of that address.

The trace data selection circuit 2 selects trace data 601 to 604 from four control units A to D in the information processing device.
is input and selectively output according to the contents of the selection signal holding register 9 to supply data to the tracer memory 1. Various examples of the control unit I-A-D can be considered, including an arithmetic unit, a control unit that controls the arithmetic unit, a microprogram address conversion unit, and various internal state management units.

The address designation circuit 3 supplies a write address that can be scanned to the tracer memory 1 unless there is a stop instruction from the stop condition detection circuit 5, and when a stop instruction is received, it holds the write address and receives a write address from the diagnostic control unit 7. A read address can be received and provided to the tracer memory 1.

The write control unit 4 supplies a predetermined write timing pulse to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and stops supplying the write timing pulse when a stop instruction is received.

The stop condition detection circuit 5 detects a predetermined write stop factor,
A stop instruction signal is supplied to the address designation circuit 3 and the write control section.

Trace data 601 to 604 represent trace data prepared by control units A to D in the information processing apparatus, respectively, and in the case of this embodiment, trace data 601 to 604
The data width of 604 is equal to 1 to the write data width of laser memory 1.

The diagnostic control unit 7 detects the tracer memory 1 in a write-stopped state.
It sends a read address to the address designation circuit 3, and also outputs an instruction signal to the selection signal holding register 9 to set and change the selection signal of the trace data.

The selection signal holding register 9 holds the contents of the selection instruction given by the diagnosis control section 7 and supplies a selection signal to the trace data selection circuit 2.

Next, the operation will be explained. When the tracer memory 1 is in the write stop state, contents for selecting and instructing the trace data 601 are set in the selection signal holding register 9 by an instruction from the diagnostic control unit 7, and when the write stop state is released, the write control unit 4 The contents of the trace data 601 are sequentially written into the tracer memory 1 via the trace data selection circuit 2 while the write address of the address designation circuit 3 changes every write timing pulse. When the stop condition detection circuit 5 detects a stop condition, it sends a stop instruction signal to the address designation circuit 3, write f, and II control section 4.

The write control unit 4 that has received the stop instruction signal stops sending out the write timing pulse, and the address designation circuit 3 holds the write address.

Therefore, writing to the tracer memory 1 is stopped. In this state, the diagnostic control unit 7 sets the read address to the addressing circuit 3.
The data is supplied to the tracer memory 1 via the tracer memory 1 and its contents are read out. After reading out all the contents, the diagnostic control section can, if necessary,
The content of the selection signal holding register 9 is changed (for example, the content of selecting the trace data 603), the write stop state is released, and writing to the tracer memory 1 is restarted.

Thereafter, the same operation will be repeated.

In the above-mentioned conventional technology, the data to be recorded as an operation history is limited in advance to a small number or is fixedly selected and written in advance, so that a sufficient operation history cannot be recorded in a large-scale information processing apparatus with a large amount of trace data. In particular, distributed control system information processing 1! [! The device has a major drawback in that the amount of operation of each control unit changes over time, so even if it is desired to flexibly change the trace data and record the operation history, it is not possible.

The present invention has been made to eliminate the drawbacks of the above-mentioned conventional methods, and its purpose is to flexibly change trace data without increasing the capacity of the laser memory. The object of the present invention is to provide an operation history storage method that allows the user to perform the following operations.

Structure of the Invention According to the present invention, in an operation history storage method in which the history of the operation content and operation state within the information processing device is stored in the storage means, inputs for a plurality of pre-selected operation fat layers are required. a trace data selection circuit that selectively outputs trace data that has been detected, and a masking unit that multiplexes and outputs a signal determined by mask information among a plurality of signals generated according to operating conditions within the information processing device. , a selection code generation circuit that receives the output signals of the masking means and generates a selection signal necessary for the selection operation of the trace data selection circuit according to a preset priority order for these signals;
There is obtained an operation history storage system characterized in that the selection output of the selection circuit and the selection signal for selecting the selection output are controlled to be written into the storage means.

Fire cover 1 FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a tracer memory 1 receives an instruction to write the output of a trace data selection circuit 2 and the output of a trace data selection code generation circuit 8 to an address determined by an address designation circuit 3. It is possible to write and store the contents of the read address designated by the diagnostic control unit 7 through the address designation circuit 3 when the write is stopped. It is possible.

The trace data selection circuit 2 inputs the 1-race data 601 to 604 from the four control units A to D in the device, and generates the contents shown in FIG. 3 according to the selection code output from the trace data selection code generation circuit 8. This outputs the following. As can be seen from Figure 3, there are five types of selection codes that are supplied, and when the selection code is binary data (the same applies hereafter) (oooo>), the control unit h
Part 60 of A-D 1-Race data 601 to 604
1a to 604a are output. Parts 6018-604
a corresponds to the most important data portion of each of the trace data 601 to 604. The selection code is (1000)
, (0100), (0010), (0
001), respectively 1~Race data 601~
604 will be output as is.

Returning to FIG. 1, the address designation circuit 3 supplies a scannable write address to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and holds the write address when a stop instruction is received. It receives the read address from the diagnostic control unit 7 and supplies it to the tracer memory 1.

The write control unit 4 supplies a predetermined write timing pulse to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and stops supplying the internal timing pulse when a stop instruction is received.

The stop condition detection circuit 5 detects a predetermined write stop factor,
The stop instruction signal is sent to the addressing circuit 3 and the write control unit 4.
supply to.

As explained earlier, trace data 601 to 604 indicate trace data from control units Δ to D in the device, and part 601a of trace data 601 represents the most important data in trace data 1301;
01b represents other data.

For example, if the trace data 601 consists of addresses and microinstructions, the address part corresponds to important data 601a, and the microinstruction part corresponds to other data 601b.

The same can be said of the trace data 602-604.

The diagnostic control unit 7 detects the tracer memory 1 in a write-stopped state.
The read address for the address is sent to the addressing circuit 3. Furthermore, the contents of the mask register 10 can be changed.

The trace data selection code generation circuit 8 inputs the output signal of the AND circuit 11 that determines the priority order of the trace data 601 to 604, and performs selection to enable output to the trace data selection circuit 2 according to the priority order. Generate and supply code signals. This selection code signal is also input to the tracer memory 1 and written therein. This is to identify which control unit the written trace data belongs to.

Figure 4 shows the trace data selection code generation circuit 8 in Figure 1.
FIG. 2 is a block diagram showing the input/output state in detail, and it can be seen that there are input signals TO to T6.

FIG. 5 shows a truth table representing the relationship between the input signal To-T6 of the data selection code generation circuit 8 and the output selection code signal, which corresponds to t in FIG. In the figure, X indicates that any value of 0.1 may be used. Referring to FIG. 5, among the input signals TO-76, the input signal TO has the highest priority, and the following T1. T2,...
It can be seen that the priority order becomes lower in the order of . For example, input signal TI.

When T4 and T6 are "1°" and all others are "0", the output selection code (1000) is determined only by the input signal T1 with the highest priority. This selection code is shown in Figure 3. This corresponds to the selection logic of the trace data selection circuit 2. Therefore, it can be seen that the input signal T1 is a signal for selecting the trace data 601 (type P1) of the h+a unit A.

The same can be said for the other To and T2 to T6. Also, when the input signals MTO to T6 are all 0, the selection code (oooo) is determined from Figure 4, and if it corresponds to Figure 3, the output of the trace data selection circuit 2 is the edit data (type PO). I know it will happen.

The mask register 10 is a register that holds a plurality of mask information QO-Q6 corresponding to a plurality of control signals SO to S6 that determine the priority order of trace data 601 to 604, and the contents can be changed by the diagnostic control unit 7. It has become.

The AND circuit 11 performs an AND operation on the control signals SO to S6 and the contents of the mask register 10 and outputs the result.
The details are shown in FIG. In FIG. 7, control signal 3
0-36 are signals that determine the priority order of the trace data 601-604, and are ANDed with the output signals MQO-Q6 from the mask register 10 to produce the output signal TO.
~T6 is supplied to the trace data selection code generation circuit.

Here, the control signals SO to S which are input to the AND circuit 11
Reference numeral 6 denotes a signal generated depending on the operating status within the Vti, for example, generated from each control unit AD, and is an operating status signal for each control unit. These control signals SO to S6, that is, signal To-76 (when not masked in any way by the mask register 10) are prioritized as explained in FIGS. 3 and 5, so the priority order is When high trace data is required, a corresponding control signal bit (one of To to T6) is generated as a logic 1 so that a selection code corresponding to the trace data is generated.

Therefore, the trace data selection code generation circuit 8 generates a selection code so as to select only the trace data corresponding to the logic 1 bit with the highest priority among these signal bits TO to T6. .

If all the control signal bits To-T6 are logic O, it can be considered that the operating states in all the control units A-D do not change and are in a waiting state, so in this case, as shown in FIG. As shown in FIG. 3, the most important parts 601a to 60 of each trace data are simply selected without selecting any of the trace data 601 to 604 of the control units A to D.
Only 4a (type PO) will be selectively introduced. In such a case, there is no need to write the i-race data to the tracer memory 1, but simply the most important part 60.
This is because the operation history of each control unit can be grasped by storing only the corresponding address portions of microinstructions 1a to 604a, for example.

The tracer memory 1 is connected to the trace data selection code generation circuit 8 while the stop condition detection circuit 5 does not detect a stop condition.
The selection code output and the output of the trace data selection circuit 2 output corresponding to the selection code are written and stored at the write address indicated by the address designation circuit when the write timing pulse by the write control unit 4 is P1''. .still,
The write address of the address designating circuit 3 is counted up every write timing pulse. When the stop condition is detected, the write address is held and no write timing pulse is generated, so the tracer memory 1 enters the write stop state, and the read address from the diagnostic control unit 7 is given via the address designation circuit 2, and the memory The current data is read out, and if it is necessary to change the mask register 11 when performing the next operation history, the mask register 11 is changed, the stop instruction is canceled, and the operation is started again.

Control signal S based on mask information of mask register 11
The purpose of masking any of O to S6 is when you want to ignore the preset priorities for these control signals SO to S6 and select trace data corresponding to control signal bits with lower priority. It's for a reason. For example, if Sl among the control signal bits is given the highest priority (bit SO is 0), the selection code will be 1000.
is obtained and trace data 601 (type P1) is selected. However, depending on the situation, there may be a case where it is desired to select trace data 603 (type P3).

In this case, mask information is set in advance in the mask register 10 so as to mask bits 30 to 32, which have a higher priority than control signal bit 83, and To to T2 are output from the AND circuit 11 as logic O It is forcibly controlled so that In this way, even more flexible selection of trace data becomes possible.

FIG. 6 shows the operation history when the capacity of the tracer memory 1 is 256 words, comparing the embodiment of the present invention (Δ) and the embodiment of the prior art (B). In the example, as shown in FIG. 6 (A>), the control signals SO to S6 in FIG. 4.5 change from (0000000) to (00000).
11) When the change changes from (0000001) to (1000001), a stop condition is detected and the tracer memory 1 is
This shows the case where writing has stopped. In other words, the latest trace data immediately before the detection of the stop condition is the control signal (10
00001) in the area of addresses 120 to 150 as type P2, and the previous trace data is stored as type P2 in the area of addresses 120 to 150 corresponding to the control signal (0000001).
It is stored as type P3 in the area 0 to 120. Similarly, the previous trace data is stored as type P1 in the areas of addresses O~50 and 230~255, and the oldest trace data is stored at address 150.
~230 is stored as type PO.

In the prior art, as shown in FIG. 6(B), this is an example of a case where the trace data 601 (type P1) is selected and written and the process is stopped. Comparing the two, it is an example of the present invention (as seen from A>, address 50
Although trace data of types P3, P2, and PO need to be written preferentially in the area from 230 to 230, the conventional technique (B) cannot change the trace data flexibly. All trace data of type P1 is written. Therefore, address 50~
The trace data of the conventional example in the area 230 cannot be said to be effective.

As explained above, according to the present invention, since the configuration is such that the operation history can be recorded while flexibly selecting trace data according to the control signal indicating the operation status within the information processing device, especially large-sized information This has the advantage that even when there is a sufficient amount of trace data, such as in a processing device or an information processing device using a distributed control method, effective operation history storage can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the prior art, FIG. 3 is a diagram showing the selection contents of the trace data selection circuit, and FIG. 4 is a diagram of the trace data selection code generation circuit. Input/output diagram, Figure 5 is a truth table showing the input/output relationship of the l/race data selection code generation circuit.
Figure 6 (A). (B) is a diagram showing an example of the operation history of the embodiment of the present invention and the conventional example, and FIG. 7 is a circuit diagram of the AND circuit in FIG. 1. Explanation of symbols of main parts 1... Tracer memory 2... Trace data selection circuit 3...
Address designation circuit 4...Write control section

Claims (1)

[Claims] An operation history storage method that stores and leaves a history of operation contents and operation states within an information processing device in a storage means, and selectively outputs input trace data for a plurality of preselected operation histories. a trace data selection circuit; a masking means for masking and outputting a signal determined by masking information among a plurality of signals generated according to operating conditions within the information processing device; and an output signal of the masking means as an input. A selection code generation circuit is provided which generates a selection signal necessary for the selection operation of the trace data selection circuit according to a preset priority order for these signals, and the selection code generation circuit generates a selection signal necessary for the selection operation of the trace data selection circuit, and the selection output of the selection circuit and this selection output are An operation history storage system characterized in that the selection signal for selection is controlled to be written into the storage means.