JPS62224840A - Operation history storage system - Google Patents

Abstract

PURPOSE:To flexibly select trace data by generating a selection signal required for selecting trace data in accordance with a present preferential order with respect to a signal generated corresponding to an operation situation in an information processor. CONSTITUTION:A tracer memory 1 writes and stores the output of a trace data selection circuit 2 and that of a trace data selection code generator circuit 8 at an address specified by an address specifying circuit 3 when a write control part 4 issues a write indication. When the memory 1 in write stoppage receives a read address specified by a diagnosis control part 7 through the circuit 3, contents at the address are read out. The input control signal of the circuit 8 is generated corresponding to the operation situation in the device from control units A-D, for instance, and is an action state signal at every control unit. Thus trace data can be flexibly modified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation history storage system in an information processing apparatus, and more particularly to a selective storage system for history data.

Ei Sarame I In recent years, information processing equipment has become larger and the machine cycles have become smaller to improve performance, so it has become difficult to control the equipment within the equipment with a single control unit, and the control unit has been decentralized. is progressing. Along with this, data to be traced is also distributed among multiple units including each control section, and the amount of data tends to increase. On the other hand, tracer memory that stores trace data is expensive, so there is a tendency not to increase the hardware size. A method of selecting the data to be loaded and ill-loading is adopted.

In FIG. 2, the tracer memory 1 is capable of storing the output of the trace data selection circuit 2 by writing it into the address designated by the address designation circuit 3 when the write control unit 4 issues a write instruction. Furthermore, when the read address designated by the diagnostic control unit 7 is received via the address designation circuit 3 when writing is in a stopped state, the contents of that address can be read out.

The trace data selection circuit 2 selects trace data 601 to 604 from four control units A to D in the information processing device.
is input and selectively output according to the contents of the selection signal holding register 9 to supply data to the tracer memory 1. Examples of the control units A to D include, among others, an arithmetic unit, a control unit that controls the arithmetic unit, a microprogram address conversion unit, and various internal state management units.

The address designation circuit 3 supplies a write address that can be scanned to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and holds the write address when a stop instruction is received, and reads it from the diagnostic control unit 7. Addresses can be received and supplied to the tracer memory 1.

The write control unit 4 supplies a predetermined write timing pulse to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and stops supplying the write timing pulse when a stop instruction is received.

The stop condition detection circuit 5 detects a predetermined write stop factor,
A stop instruction signal is supplied to the address designation circuit 3 and the write control section.

]・Race data 601 to 604 each represent trace data prepared by control units A to D in the information processing device, and in the case of this embodiment, trace data 601
The data width of 604 is equal to the write data width of the tracer memory 1.

The diagnostic control unit 7 detects the tracer memory 1 in a write-stopped state.
It sends a read address to the address designation circuit 3, and also outputs an instruction signal to the selection signal holding register 9 to set and change the selection signal of the trace data.

The selection signal holding register 9 holds the contents of the selection instruction given by the diagnosis control section 7 and supplies a selection signal to the trace data selection circuit 2.

Next, the operation will be explained. When the tracer memory 1 is in the write-stopped state, contents for selecting and instructing the trace data 601 are set in the selection signal holding register 9 according to instructions from the diagnostic control unit 7, and when the write-stopped state is released, the output control unit 4 The contents of the trace data 601 are sequentially written into the tracer memory 1 via the trace data selection circuit 2 while the write address of the address designation circuit 3 changes every write timing pulse. When the stop condition detection circuit 5 detects a stop condition, it sends a stop instruction signal to the address designation circuit 3 and write control section 4. The write control unit 4 that has received the stop instruction signal stops sending out the write timing pulse, and the address designation circuit 3 holds the write address.

Therefore, writing to the tracer memory 1 is stopped. In this state, the diagnostic control unit 7 sets the read address to the addressing circuit 3.
The data is supplied to the tracer memory 1 via the tracer memory 1 and its contents are read out. After reading out all the contents, the diagnostic control section can, if necessary,
The content of the selection signal holding register 9 is changed (for example, the content for selecting and instructing the trace data 603), the write stop state is released, and writing to the tracer memory 1 is restarted. Thereafter, the same operation will be repeated.

In the above-mentioned conventional technology, the data to be recorded as an operation history is limited in advance to a small number or is fixedly selected and written in advance, so that a sufficient operation history cannot be recorded in a large-scale information processing apparatus with a large amount of trace data. In particular, in information processing devices using a distributed control method, the operation 1 of each control unit changes over time, so even if you wanted to flexibly change the trace data and record the operation history, there was a major drawback in that it was impossible to do so. .

1. The present invention has been made to eliminate the drawbacks of the conventional ones described above, and its purpose is to make it possible to flexibly change trace data without increasing the capacity of the tracer memory. The object of the present invention is to provide an operation history storage method.

Composition of the Invention According to the present invention, there is provided an operation history storage method in which a history of operation contents and operation states within an information processing apparatus is stored in a storage means, wherein a plurality of operation history inputs selected in advance are stored. A trace data selection circuit that selectively outputs trace data; and a trace data selection circuit that receives signals generated according to operating conditions within the information processing device and selects the trace data according to preset priorities for these signals. a selection code generation circuit for generating a selection signal necessary for the selection operation of the selection circuit, and controlling writing of the selection output of the selection circuit and the selection signal for selecting the selection output into the storage means. An operation history storage method is obtained which is characterized by the following.

Example FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the tracer memory 1 outputs the output of the trace data selection circuit 2 and the output of the trace data selection code generation circuit 8 to an address specified by the address designation circuit 3 when the write control unit 4 issues a write instruction. It is possible to write and store data, and when a read address specified by the diagnostic control unit 7 is received via the address designation circuit 3 when the write is stopped, it is possible to read the contents of that address. .

The trace data selection circuit 2 inputs the trace data 601 to 604 from the four control units A to D in the device a, and outputs the contents shown in FIG. 3 according to the selection code output from the trace data selection code generation circuit 8. It is something to do. As can be seen from Fig. 3, there are five types of selection codes that are supplied, and when the selection code is binary data (the same applies hereafter) (0000), the selection code is the control unit A-D.
Parts 601a to 60 of trace data 601 to 604 of
4a is output.

Portions 601a to 604a are trace data 601 to 6
04, each corresponds to the most important data portion. The selection code is (1000), (0100), (
0010) and (0001), the trace data 601 to 604 are output as they are, respectively.

Returning to FIG. 1, the address designation circuit 3 supplies a scannable write address to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and holds the write address when a stop instruction is received. It receives the read address from the diagnostic control unit 7 and supplies it to the tracer memory 1.

The write control unit 4 supplies a predetermined write timing pulse to the tracer memory 1 when there is no stop instruction from the stop condition detection circuit 5, and stops supplying the write timing pulse when a stop instruction is received.

The stop condition detection circuit 5 detects a predetermined write stop factor,
The stop instruction signal is sent to the addressing circuit 3 and the write control unit 4.
supply to.

As described above, trace data 601 to 604 indicate trace data from control units A to D in the device, and part 601a of trace data 601 represents the most important data in trace data 601, and part 60
1b represents other data.

For example, if the trace data 601 consists of addresses and microinstructions, the address part corresponds to important data 601a, and the microinstruction part corresponds to other data 601b.

The same can be said of the trace data 602-604.

The diagnostic control unit 7 detects the tracer memory 1 in a write-stopped state.
The read address for the address is sent to the addressing circuit 3.

The trace data selection code generation circuit 8 generates a plurality of tIIJIs that determine the priority order of the trace data 601 to 604.
The Il signal is input, and a selection code signal is generated and supplied to the trace data selection circuit 2 to enable output according to the priority order. This selection code signal is also input to the tracer memory 1 and written therein. This is to identify which control unit the written trace data belongs to.

Figure 4 shows the trace data selection code generation circuit 8 in Figure 1.
FIG. 2 is a block diagram showing the input/output state in detail, and it can be seen that there are control signals SO to $6 as inputs. FIG. 5 shows a truth table representing the relationship between the control signals SO to S6, which are the inputs of the trace data selection code generation circuit 8 in FIG. 4, and the selection code signal, which is the output. In the diagram, X is 0
．． 1 Indicates that any value is acceptable.

Referring to FIG. 5, the control signal SO has the highest priority among the control signals SO to S6, and the following 31, 3
2, .

When S6 is 1'' and all others are 0'', the output selection code (1000) is determined only by the control signal S1 with the highest priority. This selection code corresponds to the selection logic of the trace data selection circuit 2 shown in FIG. Therefore,
Control signal S1 is trace data 601 of control unit A
It can be seen that this is a signal for selecting (type P1). The same can be said of the other Sos, 82 to S6. Also, when the control 1lsO-86 is all 0'', the 4th
From the figure, the selection code (0000) is determined, and when compared to FIG. 3, it can be seen that the output of the trace data selection circuit 2 is the edit data (type PO).

Here, the control signals SO to S6, which are input to the trace data selection code generation circuit 80, are signals generated depending on the operating status within the device, and are generated from each control unit A to D, for example, and are generated by the operation of each control unit. Assume that it is a status signal.

These control signals SO to S6 are prioritized as explained in FIGS. 3 and 5, so when trace data with a high priority is required, the selection corresponding to the 1-race data is The corresponding control signal bit (one of So to $6) is generated as a logic 1 so that the code is generated. Therefore, the trace data selection code generation circuit 8 generates a selection code so as to select only the trace data corresponding to the logic 1 bit with the highest priority among these control signal bits SO to S6. be.

When all control signal bits SO to S6 are logic 0, it can be considered that the operating states of all control units A to D do not change and are in a holding state, so in this case, as shown in FIG. As shown in FIG. 3, the most important parts 601a to 60 of each trace data are simply selected without selecting any of the trace data 601 to 604 of the control units A to D.
4a <type PQ) will be selectively introduced. In such a case, there is no need to write the trace data to the tray length memory 1, but simply the most important part 601a.
This is because the operation history of each control unit can be grasped by storing only the corresponding address part of the microinstruction, for example, 604a.

The tracer memory 1 is connected to the trace data selection code generation circuit 8 while the stop condition detection circuit 5 does not detect a stop condition.
The output of the selection code and the output of the trace data selection circuit 2 output corresponding to the selection code are written and stored at the write address indicated by the address designation circuit when the write timing pulse by the write control unit 4 is "1". Note that the write address of the address designation circuit 3 is counted up for each write timing pulse. When a stop condition is detected, the write address is held and no write timing pulse is generated, so the tracer memory 1 stops writing. A read address is given by the diagnostic control unit 7 via the address designation circuit 2, and the stored data is read out.

FIG. 6 shows the operation history in a case where the capacity of the tracer memory 1 is 256 words, comparing an embodiment of the present invention (A) with an embodiment of the prior art (B). In this case, as shown in FIG. 6(A), the control unit @80-86 in FIGS.
011) → (oooooooi) → (1000001)
This shows a case where a stop condition is detected and writing to the tracer memory 1 is stopped when the value changes. That is,
The latest trace data just before the stop condition was detected is the control signal (
Addresses 120-150 corresponding to 10000 (11)
The previous trace data is stored as type P2 in the area of addresses 50 to 120 corresponding to the control unit @(0000001). Similarly, the previous trace data is of type P in the area of addresses 0-50 and 230-255.
1, and the oldest trace data is stored as type PO in the area of addresses 150-230.

In the prior art, as shown in FIG. 6(B), this is an example of a case where trace data 601 (type P1) is selected and writing is stopped. Comparing the two, it can be seen from (A), which is an example of the present invention, that addresses 50 to
In the area portion of 230, type P3. Although trace data of P'2 and PO need to be written with priority, in conventional technology (B), trace data cannot be changed flexibly, so all trace data of type P1 is written. It is written. Therefore, address 50-2
The trace data of the conventional example in the area of 30 cannot be said to be effective.

As explained above, according to the present invention, since the configuration is such that the operation history can be recorded while flexibly selecting trace data according to the control signal indicating the operation status within the information processing device, especially large-sized information This has the advantage that even when there is a sufficient amount of trace data, such as in a processing device or an information processing device using a distributed control method, effective operation history storage can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the prior art, FIG. 3 is a diagram showing the selection contents of the trace data selection circuit, and FIG. 4 is a diagram of the trace data selection code generation circuit. The input/output diagram, FIG. 5, is a truth table showing the input/output relationship of the trace data selection code generation circuit, and FIG. 6(A). (B) is a diagram showing an example of operation history between the embodiment of the present invention and the conventional example. Explanation of symbols of main parts 1... Tracer memory 2... Trace data selection circuit 3...
Address designation circuit 4...Write control section

Claims (1)

[Claims] An operation history storage method that stores and leaves a history of operation contents and operation states within an information processing device in a storage means, and selectively outputs input trace data for a plurality of preselected operation histories. A trace data selection circuit receives signals generated according to operating conditions within the information processing device and makes selections necessary for the selection operation of the trace data selection circuit according to preset priorities for these signals. A selection code generation circuit that generates a signal is provided, and the selection output of the selection circuit and the selection signal for selecting the selection output are written into the storage means and controlled. method.