DE69932773T8 - Integrierte logische Halbleiterschaltung mit sequentiellen Schaltungen zur Unterdrückung von Subschwellenwert-Leckstrom - Google Patents

Integrierte logische Halbleiterschaltung mit sequentiellen Schaltungen zur Unterdrückung von Subschwellenwert-Leckstrom Download PDF

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Publication number
DE69932773T8
DE69932773T8 DE69932773T DE69932773T DE69932773T8 DE 69932773 T8 DE69932773 T8 DE 69932773T8 DE 69932773 T DE69932773 T DE 69932773T DE 69932773 T DE69932773 T DE 69932773T DE 69932773 T8 DE69932773 T8 DE 69932773T8
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Prior art keywords
suppression
sub
logic circuit
leakage current
integrated semiconductor
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Active
Application number
DE69932773T
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English (en)
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DE69932773D1 (de
DE69932773T2 (de
Inventor
Tadahiko Ogawa
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Renesas Electronics Corp
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NEC Electronics Corp
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Publication of DE69932773D1 publication Critical patent/DE69932773D1/de
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Publication of DE69932773T2 publication Critical patent/DE69932773T2/de
Publication of DE69932773T8 publication Critical patent/DE69932773T8/de
Active legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE69932773T 1998-06-12 1999-06-11 Integrierte logische Halbleiterschaltung mit sequentiellen Schaltungen zur Unterdrückung von Subschwellenwert-Leckstrom Active DE69932773T8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16517098A JP3499748B2 (ja) 1998-06-12 1998-06-12 順序回路
JP16517098 1998-06-12

Publications (3)

Publication Number Publication Date
DE69932773D1 DE69932773D1 (de) 2006-09-28
DE69932773T2 DE69932773T2 (de) 2007-08-23
DE69932773T8 true DE69932773T8 (de) 2007-12-13

Family

ID=15807198

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69932773T Active DE69932773T8 (de) 1998-06-12 1999-06-11 Integrierte logische Halbleiterschaltung mit sequentiellen Schaltungen zur Unterdrückung von Subschwellenwert-Leckstrom

Country Status (4)

Country Link
US (1) US6246265B1 (de)
EP (1) EP0964519B1 (de)
JP (1) JP3499748B2 (de)
DE (1) DE69932773T8 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3800896B2 (ja) 1999-12-03 2006-07-26 日産自動車株式会社 電磁アクチュエータの制御装置
US6549037B1 (en) * 2000-06-26 2003-04-15 Intel Corporation Apparatus and circuit having reduced leakage current and method therefor
US6476635B1 (en) * 2000-06-28 2002-11-05 Cypress Semiconductor Corp. Programmable number of metal lines and effective metal width along critical paths in a programmable logic device
US6456110B1 (en) * 2000-12-29 2002-09-24 Intel Corporation Voltage level shifter having zero DC current and state retention in drowsy mode
US7010706B2 (en) * 2001-04-13 2006-03-07 Intel Corporation Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
US6794914B2 (en) * 2002-05-24 2004-09-21 Qualcomm Incorporated Non-volatile multi-threshold CMOS latch with leakage control
KR100519787B1 (ko) * 2002-11-07 2005-10-10 삼성전자주식회사 슬립 모드에서 데이터 보존이 가능한 ｍｔｃｍｏｓ플립플롭 회로
US6934181B2 (en) * 2003-02-06 2005-08-23 International Business Machines Corporation Reducing sub-threshold leakage in a memory array
DE10323861A1 (de) * 2003-05-26 2004-12-30 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung, insbesondere zum Versetzen derselben in einen Stromsparmodus
US7170327B2 (en) * 2003-06-27 2007-01-30 Intel Corporation System and method for data retention with reduced leakage current
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
EP3537607B1 (de) * 2004-02-19 2022-11-23 MOSAID Technologies Incorporated Verlustarme datenspeicherungsschaltung
US7365596B2 (en) * 2004-04-06 2008-04-29 Freescale Semiconductor, Inc. State retention within a data processing system
KR101045295B1 (ko) * 2004-04-29 2011-06-29 삼성전자주식회사 Ｍｔｃｍｏｓ 플립-플롭, 그를 포함하는 ｍｔｃｍｏｓ회로, 및 그 생성 방법
US7221205B2 (en) * 2004-07-06 2007-05-22 Arm Limited Circuit and method for storing data in operational, diagnostic and sleep modes
US7180348B2 (en) * 2005-03-24 2007-02-20 Arm Limited Circuit and method for storing data in operational and sleep modes
US8067970B2 (en) * 2006-03-31 2011-11-29 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US8085076B2 (en) * 2008-07-03 2011-12-27 Broadcom Corporation Data retention flip flop for low power applications
US8427214B2 (en) 2010-06-03 2013-04-23 Arm Limited Clock state independent retention master-slave flip-flop
US8674739B2 (en) * 2011-02-18 2014-03-18 Oracle International Corporation Single-inversion pulse flop
JP5574461B2 (ja) * 2013-04-19 2014-08-20 ルネサスエレクトロニクス株式会社 半導体集積回路
US11386942B2 (en) 2020-08-27 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for controlling power assertion in a memory device
US20230246647A1 (en) * 2022-01-28 2023-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Power loss regulation circuit

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US4691189A (en) * 1986-05-23 1987-09-01 Rca Corporation Comparator with cascaded latches
JP3238429B2 (ja) 1991-08-20 2001-12-17 沖電気工業株式会社 半導体記憶装置
JPH05122021A (ja) 1991-10-25 1993-05-18 Nippon Telegr & Teleph Corp <Ntt> スタテイツク型トランスフアーゲート順序回路
JPH05122020A (ja) * 1991-10-25 1993-05-18 Nippon Telegr & Teleph Corp <Ntt> スタテイツク型トランスフアーゲート順序回路
JP2853726B2 (ja) 1993-12-29 1999-02-03 日本電気株式会社 Ｄ型フリップフロップ回路
US5525921A (en) * 1994-04-07 1996-06-11 Vlsi Technology, Inc. Logic suppression of input and ground spikes for synchronized inputs
DE69632098T2 (de) 1995-04-21 2005-03-24 Nippon Telegraph And Telephone Corp. MOSFET Schaltung und ihre Anwendung in einer CMOS Logikschaltung
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JP3463269B2 (ja) 1995-04-21 2003-11-05 日本電信電話株式会社 Ｍｏｓｆｅｔ回路
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KR100318327B1 (ko) 1995-12-16 2002-04-22 구광시 에멀젼형 고분자응집제의 제조방법

Also Published As

Publication number Publication date
JPH11355106A (ja) 1999-12-24
EP0964519A2 (de) 1999-12-15
US6246265B1 (en) 2001-06-12
EP0964519B1 (de) 2006-08-16
EP0964519A3 (de) 2000-10-11
JP3499748B2 (ja) 2004-02-23
DE69932773D1 (de) 2006-09-28
DE69932773T2 (de) 2007-08-23

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