DE69917950D1 - Parallel-synchrone Kopfkorrektureinrichtung für ATM - Google Patents

Parallel-synchrone Kopfkorrektureinrichtung für ATM

Info

Publication number
DE69917950D1
DE69917950D1 DE69917950T DE69917950T DE69917950D1 DE 69917950 D1 DE69917950 D1 DE 69917950D1 DE 69917950 T DE69917950 T DE 69917950T DE 69917950 T DE69917950 T DE 69917950T DE 69917950 D1 DE69917950 D1 DE 69917950D1
Authority
DE
Germany
Prior art keywords
atm
correction device
synchronous head
parallel synchronous
head correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69917950T
Other languages
English (en)
Other versions
DE69917950T2 (de
Inventor
Claude Denton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Tut Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tut Systems Inc filed Critical Tut Systems Inc
Application granted granted Critical
Publication of DE69917950D1 publication Critical patent/DE69917950D1/de
Publication of DE69917950T2 publication Critical patent/DE69917950T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/901—Wide area network
    • Y10S370/902—Packet switching
    • Y10S370/903—Osi compliant network
    • Y10S370/905—Asynchronous transfer mode, ASN

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
DE69917950T 1998-02-24 1999-01-27 Parallel-synchrone Kopfkorrektureinrichtung für ATM Expired - Lifetime DE69917950T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28717 1998-02-24
US09/028,717 US5923681A (en) 1998-02-24 1998-02-24 Parallel synchronous header correction machine for ATM

Publications (2)

Publication Number Publication Date
DE69917950D1 true DE69917950D1 (de) 2004-07-22
DE69917950T2 DE69917950T2 (de) 2005-06-23

Family

ID=21845033

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69917950T Expired - Lifetime DE69917950T2 (de) 1998-02-24 1999-01-27 Parallel-synchrone Kopfkorrektureinrichtung für ATM

Country Status (4)

Country Link
US (1) US5923681A (de)
EP (1) EP0938206B1 (de)
JP (1) JP3270966B2 (de)
DE (1) DE69917950T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100435215B1 (ko) * 1999-12-30 2004-06-09 삼성전자주식회사 버스 인코딩/디코딩 장치 및 그 방법
US6931581B1 (en) * 2000-10-25 2005-08-16 Sun Microsystems, Inc. Method for superimposing a sequence number in an error detection code in a data network
TW503636B (en) * 2001-04-12 2002-09-21 Realtek Semiconductor Corp HEC checking method and circuit for sequential feed back type cell of asynchronous transfer mode
US7443785B2 (en) 2004-03-17 2008-10-28 Sony Ericsson Mobile Communications Ab Selective error correction for ad hoc networks having multiple communication modes
CN100384118C (zh) * 2004-11-03 2008-04-23 上海贝尔阿尔卡特股份有限公司 处理通用成帧规程帧的方法和装置
DE102007035262B4 (de) * 2007-07-27 2018-05-24 Texas Instruments Deutschland Gmbh Empfänger und Verfahren zur Bearbeitung eines Datenpaketstroms bei Auftreten eines Fehlers auf der Bitübertragungsschicht
US9715432B2 (en) * 2014-12-23 2017-07-25 Intel Corporation Memory fault suppression via re-execution and hardware FSM

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678469A (en) * 1970-12-01 1972-07-18 Ibm Universal cyclic division circuit
JPS5286011A (en) * 1976-01-12 1977-07-16 Nec Corp Error correction device for parallel processing
US4397020A (en) * 1980-09-11 1983-08-02 Bell Telephone Laboratories, Incorporated Error monitoring in digital transmission systems
US4937828A (en) * 1988-11-04 1990-06-26 Westinghouse Electric Corp. High speed parallel CRC device for concatenated data frames
US5274633A (en) * 1989-11-29 1993-12-28 Fujitsu Limited Switching system for ATM dual switch system
JP2816223B2 (ja) * 1990-03-02 1998-10-27 株式会社日立製作所 セル同期回路
US5251219A (en) * 1990-09-10 1993-10-05 Advanced Micro Devices, Inc. Error detection and correction circuit
CA2059396C (en) * 1991-01-16 1996-10-22 Hiroshi Yamashita Compact device for checking a header error in asynchronous transfer mode cells
JP2655547B2 (ja) * 1991-03-13 1997-09-24 富士通株式会社 Ｃｒｃ演算方法及びａｔｍ交換方式におけるｈｅｃ同期装置
JPH04334234A (ja) * 1991-05-10 1992-11-20 Nec Corp 多重処理形ａｔｍセル誤り訂正回路
JP3069389B2 (ja) * 1991-05-27 2000-07-24 富士通株式会社 Ａｔｍセル誤り処理システム
JPH05216698A (ja) * 1991-08-05 1993-08-27 Advanced Micro Devicds Inc 改良されたエラー検出および訂正回路
ES2100269T3 (es) * 1992-07-14 1997-06-16 Alcatel Bell Nv Dispositivo de deteccion y correccion de error.
ES2068105B1 (es) * 1992-11-30 1995-11-01 Alcatel Standard Electrica Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.
JP2999342B2 (ja) * 1993-03-19 2000-01-17 富士通株式会社 Ａｔｍ伝送システムにおけるパスルート試験方式
NL9301156A (nl) * 1993-07-01 1995-02-01 Nederland Ptt ATM Celdetector.
FR2707819B1 (fr) * 1993-07-12 1995-09-15 Tremel Jean Yves Procédé et dispositif de surveillance et/ou de test d'un réseau de télécommunication de type ATM.
US5487061A (en) * 1994-06-27 1996-01-23 Loral Fairchild Corporation System and method for providing multiple loss and service priorities
US5745507A (en) * 1995-03-31 1998-04-28 International Business Machines Corporation Systematic symbol level ECC for use in digital memory systems

Also Published As

Publication number Publication date
EP0938206B1 (de) 2004-06-16
DE69917950T2 (de) 2005-06-23
EP0938206A2 (de) 1999-08-25
EP0938206A3 (de) 2001-06-13
JP3270966B2 (ja) 2002-04-02
JPH11284641A (ja) 1999-10-15
US5923681A (en) 1999-07-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806