ES2100269T3 - Dispositivo de deteccion y correccion de error. - Google Patents

Dispositivo de deteccion y correccion de error.

Info

Publication number
ES2100269T3
ES2100269T3 ES92202148T ES92202148T ES2100269T3 ES 2100269 T3 ES2100269 T3 ES 2100269T3 ES 92202148 T ES92202148 T ES 92202148T ES 92202148 T ES92202148 T ES 92202148T ES 2100269 T3 ES2100269 T3 ES 2100269T3
Authority
ES
Spain
Prior art keywords
sequence
bus
bit
circuit
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92202148T
Other languages
English (en)
Inventor
Werner Jozef Catharin Stessens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Alcatel Lucent NV
Original Assignee
Alcatel Bell NV
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Bell NV, Alcatel NV filed Critical Alcatel Bell NV
Application granted granted Critical
Publication of ES2100269T3 publication Critical patent/ES2100269T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Geophysics And Detection Of Objects (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Closed-Circuit Television Systems (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

EL DISPOSITIVO DE DETECCION Y CORRECCION DE ERRORES DETECTA Y CORRIGE LOS ERRORES DE UN SOLO BIT DE UNA SECUENCIA DE BITS QUE CONTIENE UNA PLURALIDAD DE SUBGRUPOS DE N BITS COLOCADOS EN UN BUS PARALELO IN QUE TIENE M PARTES DEL SUBGRUPO. INCLUYE UN MODULO DE ALMACENAMIENTO ST CONECTADO AL BUS IN Y QUE TRANSFIERE LOS SUBGRUPOS A MEDIDA QUE EL BUS LOS VA RECIBIENDO A UN CIRCUITO LOGICO DIVISOR DL. ESTE CIRCUITO LLEVA A CABO UNA DIVISION DEL MODULO PARALELO DE M*N BITS 2 DE LA SECUENCIA RECIBIDA ENTRE UN POLINOMIO DADO Y TRASFIERE EL RESTO REM A UN CIRCUITO DE COMPARACION C DONDE ES COMPARADO CON UN BYTE CERO O CON UN BYTE DE CODIGO DE ERROR HEC QUE SE ENCUENTRA EN LA SECUENCIA DEPENDIENDO DE LA POSICION DEL PRIMER BYTE DE LA SECUENCIA DEL BUS. EN BASE AL RESULTADO DE LA COMPARACION Y MEDIANTE LAS UTILIZACION DE UNAS TABLAS DE TRADUCCION, UN CIRCUITO PROCESADOR PR DETERMINA LA POSICION DEL BIT EN LA SECUENCIA DE UN ERROR DE BIT. UN CIRCUITO LOGICO DE CORRECCION CL CORRIGE LA SECUENCIA RECIBIDA.
ES92202148T 1992-07-14 1992-07-14 Dispositivo de deteccion y correccion de error. Expired - Lifetime ES2100269T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92202148A EP0582749B1 (en) 1992-07-14 1992-07-14 Error detection and correction device

Publications (1)

Publication Number Publication Date
ES2100269T3 true ES2100269T3 (es) 1997-06-16

Family

ID=8210774

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92202148T Expired - Lifetime ES2100269T3 (es) 1992-07-14 1992-07-14 Dispositivo de deteccion y correccion de error.

Country Status (8)

Country Link
US (1) US5402429A (es)
EP (1) EP0582749B1 (es)
JP (1) JP3249645B2 (es)
AT (1) ATE149763T1 (es)
AU (1) AU664284B2 (es)
CA (1) CA2100387C (es)
DE (1) DE69217931T2 (es)
ES (1) ES2100269T3 (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2068105B1 (es) * 1992-11-30 1995-11-01 Alcatel Standard Electrica Metodo y dispositivo de deteccion y correccion de errores en cabeceras de celulas atm.
JPH06242977A (ja) * 1993-02-16 1994-09-02 Mitsubishi Electric Corp １チップマイクロプロセッサ
JP3454962B2 (ja) * 1995-03-23 2003-10-06 株式会社東芝 誤り訂正符号の符号器及び復号器
US5774480A (en) * 1995-10-10 1998-06-30 Allied Telesyn International Corporation Cyclic code check bits generation and error correction using sum of remainders
US5812556A (en) * 1996-07-03 1998-09-22 General Signal Corporation Fault tolerant switch fabric with control and data correction by hamming codes and error inducing check register
US5805614A (en) * 1996-07-03 1998-09-08 General Signal Corporation Fault tolerant switch fabric with control and data correction by hamming codes
GB2321374A (en) * 1997-01-21 1998-07-22 Ico Services Ltd Spread spectrum satellite communication
US5923681A (en) * 1998-02-24 1999-07-13 Tektronix, Inc. Parallel synchronous header correction machine for ATM
KR100579088B1 (ko) * 1998-12-29 2006-11-30 두산인프라코어 주식회사 전송에러의 검출과 정정이 가능한 데이터 통신시스템 및 에러정정방법
US6968492B1 (en) 2002-03-28 2005-11-22 Annadurai Andy P Hardware-efficient CRC generator for high speed communication networks
US20050114751A1 (en) * 2003-11-24 2005-05-26 Ungstad Steve J. Two input differential cyclic accumulator
US7904760B2 (en) * 2005-07-06 2011-03-08 Cisco Technology, Inc. Method and system for using presence information in error notification
US8286059B1 (en) 2007-01-08 2012-10-09 Marvell International Ltd. Word-serial cyclic code encoder
US8644434B2 (en) * 2011-09-22 2014-02-04 Lsi Corporation Apparatus and methods for performing sequence detection

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678469A (en) * 1970-12-01 1972-07-18 Ibm Universal cyclic division circuit
JPS5286011A (en) * 1976-01-12 1977-07-16 Nec Corp Error correction device for parallel processing
US4473902A (en) * 1982-04-22 1984-09-25 Sperrt Corporation Error correcting code processing system
US4712215A (en) * 1985-12-02 1987-12-08 Advanced Micro Devices, Inc. CRC calculation machine for separate calculation of checkbits for the header packet and data packet
JPH01150940A (ja) * 1987-12-08 1989-06-13 Hitachi Ltd Ｃｒｃ演算方式
US4937828A (en) * 1988-11-04 1990-06-26 Westinghouse Electric Corp. High speed parallel CRC device for concatenated data frames
JP2592681B2 (ja) * 1989-09-11 1997-03-19 日本電信電話株式会社 セル同期回路
IT1241429B (it) * 1990-03-01 1994-01-17 Sip Circuito elettronico per la generazione di codici per la rilevazione di errori in segnali numerici
JP2555906B2 (ja) * 1990-05-18 1996-11-20 日本電気株式会社 Ａｔｍセルのｖｃｉ変換方式
NO170560C (no) * 1990-05-29 1992-10-28 Alcatel Stk As Atm celledelineator
CA2049910C (en) * 1990-08-27 1999-02-09 Yoshihiro Uchida Apparatus for testing atm channels
CA2055172A1 (en) * 1990-12-10 1992-06-11 Joseph H. Condon Error detection and framing in packets transmitted in a sequence of fixed-length cells
CA2059396C (en) * 1991-01-16 1996-10-22 Hiroshi Yamashita Compact device for checking a header error in asynchronous transfer mode cells

Also Published As

Publication number Publication date
DE69217931D1 (de) 1997-04-10
ATE149763T1 (de) 1997-03-15
CA2100387C (en) 1998-05-19
JP3249645B2 (ja) 2002-01-21
EP0582749B1 (en) 1997-03-05
CA2100387A1 (en) 1994-01-15
US5402429A (en) 1995-03-28
AU4173393A (en) 1994-01-20
DE69217931T2 (de) 1997-09-25
AU664284B2 (en) 1995-11-09
EP0582749A1 (en) 1994-02-16
JPH06188747A (ja) 1994-07-08

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