DE69906156D1 - Mikroprozessorvorrichtung mit programmierbaren wartezuständen - Google Patents
Mikroprozessorvorrichtung mit programmierbaren wartezuständenInfo
- Publication number
- DE69906156D1 DE69906156D1 DE69906156T DE69906156T DE69906156D1 DE 69906156 D1 DE69906156 D1 DE 69906156D1 DE 69906156 T DE69906156 T DE 69906156T DE 69906156 T DE69906156 T DE 69906156T DE 69906156 D1 DE69906156 D1 DE 69906156D1
- Authority
- DE
- Germany
- Prior art keywords
- wait state
- microprocessor device
- programmable wait
- programmable
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/266,045 US6356987B1 (en) | 1999-03-10 | 1999-03-10 | Microprocessing device having programmable wait states |
PCT/US1999/029321 WO2000054165A1 (en) | 1999-03-10 | 1999-12-09 | Microprocessing device having programmable wait states |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69906156D1 true DE69906156D1 (de) | 2003-04-24 |
DE69906156T2 DE69906156T2 (de) | 2003-11-27 |
Family
ID=23012935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69906156T Expired - Lifetime DE69906156T2 (de) | 1999-03-10 | 1999-12-09 | Mikroprozessorvorrichtung mit programmierbaren wartezuständen |
Country Status (12)
Country | Link |
---|---|
US (1) | US6356987B1 (de) |
EP (1) | EP1163598B1 (de) |
JP (1) | JP2002539527A (de) |
KR (1) | KR100660448B1 (de) |
CN (1) | CN1120430C (de) |
CA (1) | CA2363085A1 (de) |
DE (1) | DE69906156T2 (de) |
HK (1) | HK1041073B (de) |
MY (1) | MY133914A (de) |
NO (1) | NO321931B1 (de) |
TW (1) | TW518501B (de) |
WO (1) | WO2000054165A1 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407949B1 (en) * | 1999-12-17 | 2002-06-18 | Qualcomm, Incorporated | Mobile communication device having integrated embedded flash and SRAM memory |
JP2002091905A (ja) * | 2000-09-20 | 2002-03-29 | Mitsubishi Electric Corp | 半導体装置およびアクセスウェイト数変更プログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6662285B1 (en) * | 2001-01-09 | 2003-12-09 | Xilinx, Inc. | User configurable memory system having local and global memory blocks |
ITTO20010333A1 (it) * | 2001-04-06 | 2002-10-06 | St Microelectronics Srl | Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile. |
US6605962B2 (en) | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
US7076595B1 (en) * | 2001-05-18 | 2006-07-11 | Xilinx, Inc. | Programmable logic device including programmable interface core and central processing unit |
US6798239B2 (en) * | 2001-09-28 | 2004-09-28 | Xilinx, Inc. | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry |
US7420392B2 (en) * | 2001-09-28 | 2008-09-02 | Xilinx, Inc. | Programmable gate array and embedded circuitry initialization and processing |
US6781407B2 (en) | 2002-01-09 | 2004-08-24 | Xilinx, Inc. | FPGA and embedded circuitry initialization and processing |
US6983405B1 (en) | 2001-11-16 | 2006-01-03 | Xilinx, Inc., | Method and apparatus for testing circuitry embedded within a field programmable gate array |
US6996758B1 (en) | 2001-11-16 | 2006-02-07 | Xilinx, Inc. | Apparatus for testing an interconnecting logic fabric |
US6886092B1 (en) | 2001-11-19 | 2005-04-26 | Xilinx, Inc. | Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion |
JP3510618B2 (ja) * | 2002-02-05 | 2004-03-29 | 沖電気工業株式会社 | バスブリッジ回路及びそのアクセス制御方法 |
US6820248B1 (en) | 2002-02-14 | 2004-11-16 | Xilinx, Inc. | Method and apparatus for routing interconnects to devices with dissimilar pitches |
US6754882B1 (en) | 2002-02-22 | 2004-06-22 | Xilinx, Inc. | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
US6976160B1 (en) | 2002-02-22 | 2005-12-13 | Xilinx, Inc. | Method and system for controlling default values of flip-flops in PGA/ASIC-based designs |
US7007121B1 (en) | 2002-02-27 | 2006-02-28 | Xilinx, Inc. | Method and apparatus for synchronized buses |
US6934922B1 (en) | 2002-02-27 | 2005-08-23 | Xilinx, Inc. | Timing performance analysis |
US6839874B1 (en) | 2002-02-28 | 2005-01-04 | Xilinx, Inc. | Method and apparatus for testing an embedded device |
US7111217B1 (en) | 2002-02-28 | 2006-09-19 | Xilinx, Inc. | Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) |
US7111220B1 (en) | 2002-03-01 | 2006-09-19 | Xilinx, Inc. | Network physical layer with embedded multi-standard CRC generator |
US7088767B1 (en) | 2002-03-01 | 2006-08-08 | Xilinx, Inc. | Method and apparatus for operating a transceiver in different data rates |
US7187709B1 (en) | 2002-03-01 | 2007-03-06 | Xilinx, Inc. | High speed configurable transceiver architecture |
US6961919B1 (en) | 2002-03-04 | 2005-11-01 | Xilinx, Inc. | Method of designing integrated circuit having both configurable and fixed logic circuitry |
US6973405B1 (en) | 2002-05-22 | 2005-12-06 | Xilinx, Inc. | Programmable interactive verification agent |
US6772405B1 (en) | 2002-06-13 | 2004-08-03 | Xilinx, Inc. | Insertable block tile for interconnecting to a device embedded in an integrated circuit |
US7085973B1 (en) | 2002-07-09 | 2006-08-01 | Xilinx, Inc. | Testing address lines of a memory controller |
US7099426B1 (en) | 2002-09-03 | 2006-08-29 | Xilinx, Inc. | Flexible channel bonding and clock correction operations on a multi-block data path |
US7092865B1 (en) | 2002-09-10 | 2006-08-15 | Xilinx, Inc. | Method and apparatus for timing modeling |
US7421014B2 (en) * | 2003-09-11 | 2008-09-02 | Xilinx, Inc. | Channel bonding of a plurality of multi-gigabit transceivers |
EP1866777A4 (de) * | 2005-03-30 | 2008-03-26 | Atmel Corp | Verfahren und vorrichtung zur verringerung von systeminaktivität während einer zeitdaten-float-verzögerung und eines externen speicherschreibvorgangs |
US7269704B2 (en) * | 2005-03-30 | 2007-09-11 | Atmel Corporation | Method and apparatus for reducing system inactivity during time data float delay and external memory write |
US7405949B2 (en) * | 2005-12-09 | 2008-07-29 | Samsung Electronics Co., Ltd. | Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices |
KR101131919B1 (ko) * | 2005-12-09 | 2012-04-03 | 삼성전자주식회사 | 메모리 시스템 및 이 시스템의 신호 송수신 방법 |
US9405720B2 (en) | 2013-03-15 | 2016-08-02 | Atmel Corporation | Managing wait states for memory access |
JP6326671B2 (ja) * | 2013-10-03 | 2018-05-23 | 株式会社エルイーテック | プロセッサへのwait挿入 |
JP2021047967A (ja) * | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | 半導体デバイス |
FR3111439B1 (fr) * | 2020-06-12 | 2023-06-30 | St Microelectronics Rousset | Procédé de gestion des requêtes d’accès à une mémoire vive et système correspondant |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02235156A (ja) | 1989-03-08 | 1990-09-18 | Canon Inc | 情報処理装置 |
JPH03210649A (ja) | 1990-01-12 | 1991-09-13 | Fujitsu Ltd | マイクロコンピュータおよびそのバスサイクル制御方法 |
US5313621A (en) | 1990-05-18 | 1994-05-17 | Zilog, Inc. | Programmable wait states generator for a microprocessor and computer system utilizing it |
EP0660329B1 (de) * | 1993-12-16 | 2003-04-09 | Mosaid Technologies Incorporated | Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher |
US5732250A (en) | 1994-09-15 | 1998-03-24 | Intel Corporation | Multi-function microprocessor wait state mechanism using external control line |
JPH08147161A (ja) | 1994-11-21 | 1996-06-07 | Nec Corp | データ処理装置 |
US6023776A (en) * | 1996-03-22 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Central processing unit having a register which store values to vary wait cycles |
US5854944A (en) * | 1996-05-09 | 1998-12-29 | Motorola, Inc. | Method and apparatus for determining wait states on a per cycle basis in a data processing system |
-
1999
- 1999-03-10 US US09/266,045 patent/US6356987B1/en not_active Expired - Lifetime
- 1999-12-09 WO PCT/US1999/029321 patent/WO2000054165A1/en active IP Right Grant
- 1999-12-09 EP EP99964203A patent/EP1163598B1/de not_active Expired - Lifetime
- 1999-12-09 CA CA002363085A patent/CA2363085A1/en not_active Abandoned
- 1999-12-09 DE DE69906156T patent/DE69906156T2/de not_active Expired - Lifetime
- 1999-12-09 CN CN99816463A patent/CN1120430C/zh not_active Expired - Fee Related
- 1999-12-09 KR KR1020017011334A patent/KR100660448B1/ko not_active IP Right Cessation
- 1999-12-09 JP JP2000604322A patent/JP2002539527A/ja not_active Ceased
- 1999-12-23 MY MYPI99005708A patent/MY133914A/en unknown
- 1999-12-30 TW TW088123306A patent/TW518501B/zh not_active IP Right Cessation
-
2001
- 2001-08-31 NO NO20014246A patent/NO321931B1/no not_active IP Right Cessation
-
2002
- 2002-04-17 HK HK02102907.6A patent/HK1041073B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
NO321931B1 (no) | 2006-07-24 |
NO20014246L (no) | 2001-08-31 |
CA2363085A1 (en) | 2000-09-14 |
EP1163598B1 (de) | 2003-03-19 |
CN1120430C (zh) | 2003-09-03 |
EP1163598A1 (de) | 2001-12-19 |
JP2002539527A (ja) | 2002-11-19 |
US6356987B1 (en) | 2002-03-12 |
DE69906156T2 (de) | 2003-11-27 |
HK1041073A1 (en) | 2002-06-28 |
CN1338076A (zh) | 2002-02-27 |
KR100660448B1 (ko) | 2006-12-22 |
WO2000054165A1 (en) | 2000-09-14 |
KR20010104721A (ko) | 2001-11-26 |
MY133914A (en) | 2007-11-30 |
NO20014246D0 (no) | 2001-08-31 |
HK1041073B (zh) | 2004-05-14 |
TW518501B (en) | 2003-01-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |