DE69841696D1 - Verfahren zur herstellung von hsq-schichten und von grenzenlosen vias mit strukturierten metallschichten wobei die öffnungen mit hsq gefüllt sind - Google Patents

Verfahren zur herstellung von hsq-schichten und von grenzenlosen vias mit strukturierten metallschichten wobei die öffnungen mit hsq gefüllt sind

Info

Publication number
DE69841696D1
DE69841696D1 DE69841696T DE69841696T DE69841696D1 DE 69841696 D1 DE69841696 D1 DE 69841696D1 DE 69841696 T DE69841696 T DE 69841696T DE 69841696 T DE69841696 T DE 69841696T DE 69841696 D1 DE69841696 D1 DE 69841696D1
Authority
DE
Germany
Prior art keywords
hsq
layers
limitless
vias
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841696T
Other languages
German (de)
English (en)
Inventor
Robert C Chen
Jeffrey A Shields
Robert Dawson
Khanh Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Application granted granted Critical
Publication of DE69841696D1 publication Critical patent/DE69841696D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6925—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
DE69841696T 1997-10-16 1998-10-16 Verfahren zur herstellung von hsq-schichten und von grenzenlosen vias mit strukturierten metallschichten wobei die öffnungen mit hsq gefüllt sind Expired - Lifetime DE69841696D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/951,592 US5866945A (en) 1997-10-16 1997-10-16 Borderless vias with HSQ gap filled patterned metal layers
PCT/US1998/022040 WO1999019904A1 (en) 1997-10-16 1998-10-16 Borderless vias with hsq gap filled patterned metal layers

Publications (1)

Publication Number Publication Date
DE69841696D1 true DE69841696D1 (de) 2010-07-15

Family

ID=25491880

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841696T Expired - Lifetime DE69841696D1 (de) 1997-10-16 1998-10-16 Verfahren zur herstellung von hsq-schichten und von grenzenlosen vias mit strukturierten metallschichten wobei die öffnungen mit hsq gefüllt sind

Country Status (6)

Country Link
US (2) US5866945A (https=)
EP (1) EP1029344B1 (https=)
JP (1) JP4422326B2 (https=)
KR (1) KR100550304B1 (https=)
DE (1) DE69841696D1 (https=)
WO (1) WO1999019904A1 (https=)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218078B1 (en) * 1997-09-24 2001-04-17 Advanced Micro Devices, Inc. Creation of an etch hardmask by spin-on technique
US6071824A (en) * 1997-09-25 2000-06-06 Advanced Micro Devices, Inc. Method and system for patterning to enhance performance of a metal layer of a semiconductor device
JP3277990B2 (ja) * 1997-10-23 2002-04-22 日本電気株式会社 半導体装置の製造方法
US6133142A (en) * 1997-12-18 2000-10-17 Advanced Micro Devices, Inc. Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias
US6180534B1 (en) * 1997-12-18 2001-01-30 Advanced Micro Devices, Inc. Borderless vias without degradation of HSQ gap fill layers
US5942801A (en) * 1997-12-18 1999-08-24 Advanced Micro Devices, Inc. Borderless vias with HSQ gap filled metal patterns having high etching resistance
US6020266A (en) * 1997-12-31 2000-02-01 Intel Corporation Single step electroplating process for interconnect via fill and metal line patterning
US6046104A (en) * 1998-05-15 2000-04-04 Advanced Micro Devices, Inc. Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias
US6350673B1 (en) * 1998-08-13 2002-02-26 Texas Instruments Incorporated Method for decreasing CHC degradation
US6169040B1 (en) * 1998-10-20 2001-01-02 Rohm Co., Ltd. Method of manufacturing semiconductor device
TW399285B (en) * 1998-12-04 2000-07-21 United Microelectronics Corp Method for manufacturing inter-metal dielectric layer
US6140706A (en) * 1998-12-08 2000-10-31 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers
GB9904427D0 (en) 1999-02-26 1999-04-21 Trikon Holdings Ltd Method treating an insulating layer
JP2000286254A (ja) * 1999-03-31 2000-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6596639B1 (en) * 1999-10-08 2003-07-22 Agere Systems Inc. Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials
US6403464B1 (en) 1999-11-03 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to reduce the moisture content in an organic low dielectric constant material
US6531389B1 (en) * 1999-12-20 2003-03-11 Taiwan Semiconductor Manufacturing Company Method for forming incompletely landed via with attenuated contact resistance
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6913796B2 (en) * 2000-03-20 2005-07-05 Axcelis Technologies, Inc. Plasma curing process for porous low-k materials
US6268294B1 (en) * 2000-04-04 2001-07-31 Taiwan Semiconductor Manufacturing Company Method of protecting a low-K dielectric material
US6436808B1 (en) 2000-12-07 2002-08-20 Advanced Micro Devices, Inc. NH3/N2-plasma treatment to prevent organic ILD degradation
US6713382B1 (en) * 2001-01-31 2004-03-30 Advanced Micro Devices, Inc. Vapor treatment for repairing damage of low-k dielectric
US6455409B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Damascene processing using a silicon carbide hard mask
US6518646B1 (en) 2001-03-29 2003-02-11 Advanced Micro Devices, Inc. Semiconductor device with variable composition low-k inter-layer dielectric and method of making
US6645864B1 (en) 2002-02-05 2003-11-11 Taiwan Semiconductor Manufacturing Company Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning
US6770566B1 (en) 2002-03-06 2004-08-03 Cypress Semiconductor Corporation Methods of forming semiconductor structures, and articles and devices formed thereby
US6933246B2 (en) * 2002-06-14 2005-08-23 Trikon Technologies Limited Dielectric film
US7005390B2 (en) * 2002-10-09 2006-02-28 Intel Corporation Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials
US20040099283A1 (en) * 2002-11-26 2004-05-27 Axcelis Technologies, Inc. Drying process for low-k dielectric films
US7524735B1 (en) 2004-03-25 2009-04-28 Novellus Systems, Inc Flowable film dielectric gap fill process
US7582555B1 (en) * 2005-12-29 2009-09-01 Novellus Systems, Inc. CVD flowable gap fill
US9257302B1 (en) 2004-03-25 2016-02-09 Novellus Systems, Inc. CVD flowable gap fill
US7235489B2 (en) * 2004-05-21 2007-06-26 Agere Systems Inc. Device and method to eliminate shorting induced by via to metal misalignment
JP4223012B2 (ja) 2005-02-09 2009-02-12 富士通マイクロエレクトロニクス株式会社 絶縁膜の形成方法、多層構造の形成方法および半導体装置の製造方法
US9245739B2 (en) 2006-11-01 2016-01-26 Lam Research Corporation Low-K oxide deposition by hydrolysis and condensation
US8557712B1 (en) 2008-12-15 2013-10-15 Novellus Systems, Inc. PECVD flowable dielectric gap fill
US8278224B1 (en) 2009-09-24 2012-10-02 Novellus Systems, Inc. Flowable oxide deposition using rapid delivery of process gases
TWI579916B (zh) * 2009-12-09 2017-04-21 諾菲勒斯系統公司 整合可流動氧化物及頂蓋氧化物之新穎間隙填充
US8685867B1 (en) 2010-12-09 2014-04-01 Novellus Systems, Inc. Premetal dielectric integration process
US9719169B2 (en) 2010-12-20 2017-08-01 Novellus Systems, Inc. System and apparatus for flowable deposition in semiconductor fabrication
US8846536B2 (en) 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US9847222B2 (en) 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US10049921B2 (en) 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US9916977B2 (en) 2015-11-16 2018-03-13 Lam Research Corporation Low k dielectric deposition via UV driven photopolymerization
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric
US10741495B2 (en) * 2018-01-18 2020-08-11 Globalfoundries Inc. Structure and method to reduce shorts and contact resistance in semiconductor devices
CN113728415B (zh) 2019-04-19 2025-05-16 朗姆研究公司 原子层沉积期间的快速冲洗清扫
US11101128B1 (en) * 2020-03-12 2021-08-24 Applied Materials, Inc. Methods for gapfill in substrates

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3174416B2 (ja) * 1992-12-10 2001-06-11 ダウ・コ−ニング・コ−ポレ−ション 酸化ケイ素膜の形成方法
TW347149U (en) * 1993-02-26 1998-12-01 Dow Corning Integrated circuits protected from the environment by ceramic and barrier metal layers
US5441765A (en) * 1993-09-22 1995-08-15 Dow Corning Corporation Method of forming Si-O containing coatings
JP3214186B2 (ja) * 1993-10-07 2001-10-02 三菱電機株式会社 半導体装置の製造方法
US6423651B1 (en) * 1993-12-27 2002-07-23 Kawasaki Steel Corporation Insulating film of semiconductor device and coating solution for forming insulating film and method of manufacturing insulating film
JP2751820B2 (ja) * 1994-02-28 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5456952A (en) * 1994-05-17 1995-10-10 Lsi Logic Corporation Process of curing hydrogen silsesquioxane coating to form silicon oxide layer
EP0701277B1 (en) * 1994-05-27 2008-02-27 Texas Instruments Incorporated Interconnection method using a porous insulator for line to line capacitance reduction
US5534731A (en) * 1994-10-28 1996-07-09 Advanced Micro Devices, Incorporated Layered low dielectric constant technology
US5530293A (en) * 1994-11-28 1996-06-25 International Business Machines Corporation Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits
KR19980035517A (ko) * 1996-11-14 1998-08-05 김상종 에폭시(epoxy)를 활용한 돌출칼라문자(그림)의 제조방법

Also Published As

Publication number Publication date
KR100550304B1 (ko) 2006-02-08
EP1029344A1 (en) 2000-08-23
JP4422326B2 (ja) 2010-02-24
US6060384A (en) 2000-05-09
EP1029344B1 (en) 2010-06-02
JP2001520459A (ja) 2001-10-30
WO1999019904A1 (en) 1999-04-22
KR20010031049A (ko) 2001-04-16
US5866945A (en) 1999-02-02

Similar Documents

Publication Publication Date Title
DE69841696D1 (de) Verfahren zur herstellung von hsq-schichten und von grenzenlosen vias mit strukturierten metallschichten wobei die öffnungen mit hsq gefüllt sind
DE69829181D1 (de) Verbesserte trennsäulen und verfahren zur herstellung der verbesserten trennsäulen
DE69840337D1 (de) Verfahren zur herstellung von leistungshalbleiterbauelementen mit zusammengebundenen körperwannen und dadurch hergestellte bauelementen
DE69406020D1 (de) Verfahren zur herstellung von strukturen mit mikrokanälen/mikrohohlräumen
DE69822827D1 (de) Verfahren zur herstellung von mehrkomponentigen und mehrlagigen vliesstoffen
DE69913247D1 (de) Organisch-inorganisch leitfähiger Verbundmaterial-Sol und Verfahren zur Herstellung desselben
EP0783727A4 (en) MICROSTRUCTURES AND METHOD FOR MANUFACTURING MICROSTRUCTURES
DE69530954D1 (de) Mikromechanisches Bauelement und Verfahren zur Herstellung desselben
DE69532184D1 (de) Schlüssel mit elektronischem Bauelement und Verfahren zu seiner Herstellung
DE69415717D1 (de) Schicht aus Verbundwerkstoff und Verfahren, um sie Herzustellen
DE69808139D1 (de) Verfahren zum herstellen und verrohren von ölproduktionsbohrlöchern
DE69405435D1 (de) Verfahren und Vorrichtung für die Herstellung von elektrisch zusammengeschalteten Schaltungen
DE69522324D1 (de) Farblampe und verfahren zur herstellung derselben
DE69825253D1 (de) Verfahren für die herstellung von 1,1,1,3,3-pentafluorpropen und 2-chlor-pentafluorpropen
AT377944B (de) Schichtverbundwerkstoff und verfahren zu seiner herstellung
DE10295883T1 (de) Mit einem isolierenden Bauteil ausgestatteter Kern und Verfahren zur Herstellung desselben
DE69012731D1 (de) Oxydsupraleiter und verfahren zur herstellung.
DE69833756D1 (de) Elektronisches bauelement und verfahren zu seiner herstellung
DE69511225D1 (de) Festelektrolytkondensator mit wärmebeständigem Polyanilin und Verfahren zur Herstellung desselben
DE69531196D1 (de) Vorrichtung und verfahren zur herstellung von transmissionshologrammen
DE59405660D1 (de) VERFAHREN ZUR HERSTELLUNG VON TiN-SINTERKÖRPERN UND -SCHICHTEN
DE69224423D1 (de) Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-Schichtstruktur
DE69415569D1 (de) Verfahren und Gerät zur Herstellung von verstärkten Lagen
DE69809248D1 (de) Farbstoffzwischenverbindungen und verfahren zur herstellung von farstoffen
DE69513660D1 (de) Verfahren zur herstellung von mehrschichtlackierungen, basisschichtzusammensetzung sowie verfahren zur lackierung