DE69824368D1 - Herstellungsverfahren einer halbleitervorrichtung mit flacher grabenisolation - Google Patents

Herstellungsverfahren einer halbleitervorrichtung mit flacher grabenisolation

Info

Publication number
DE69824368D1
DE69824368D1 DE69824368T DE69824368T DE69824368D1 DE 69824368 D1 DE69824368 D1 DE 69824368D1 DE 69824368 T DE69824368 T DE 69824368T DE 69824368 T DE69824368 T DE 69824368T DE 69824368 D1 DE69824368 D1 DE 69824368D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
trench insulation
flat trench
flat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69824368T
Other languages
English (en)
Other versions
DE69824368T2 (de
Inventor
Hermanus Woerlee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority claimed from PCT/IB1998/000281 external-priority patent/WO1998045877A1/en
Publication of DE69824368D1 publication Critical patent/DE69824368D1/de
Application granted granted Critical
Publication of DE69824368T2 publication Critical patent/DE69824368T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
DE69824368T 1997-04-07 1998-03-05 Herstellungsverfahren einer halbleitervorrichtung mit flacher grabenisolation Expired - Lifetime DE69824368T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97201020 1997-04-07
EP97201020 1997-04-07
PCT/IB1998/000281 WO1998045877A1 (en) 1997-04-07 1998-03-05 Method of manufacturing a semiconductor device having 'shallow trench isolation'

Publications (2)

Publication Number Publication Date
DE69824368D1 true DE69824368D1 (de) 2004-07-15
DE69824368T2 DE69824368T2 (de) 2005-06-16

Family

ID=8228178

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69824368T Expired - Lifetime DE69824368T2 (de) 1997-04-07 1998-03-05 Herstellungsverfahren einer halbleitervorrichtung mit flacher grabenisolation

Country Status (3)

Country Link
US (1) US5966616A (de)
JP (1) JP4145359B2 (de)
DE (1) DE69824368T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780346A (en) * 1996-12-31 1998-07-14 Intel Corporation N2 O nitrided-oxide trench sidewalls and method of making isolation structure
JP3967440B2 (ja) * 1997-12-09 2007-08-29 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6555476B1 (en) * 1997-12-23 2003-04-29 Texas Instruments Incorporated Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric
KR100275732B1 (ko) * 1998-05-22 2000-12-15 윤종용 어닐링을 이용한 트랜치형 소자분리막 형성방법
US6759306B1 (en) 1998-07-10 2004-07-06 Micron Technology, Inc. Methods of forming silicon dioxide layers and methods of forming trench isolation regions
US6335235B1 (en) * 1999-08-17 2002-01-01 Advanced Micro Devices, Inc. Simplified method of patterning field dielectric regions in a semiconductor device
JP2001085511A (ja) * 1999-09-14 2001-03-30 Toshiba Corp 素子分離方法
JP2006310625A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体記憶装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5643825A (en) * 1994-12-29 1997-07-01 Advanced Micro Devices, Inc. Integrated circuit isolation process
JPH11162185A (ja) * 1997-11-25 1999-06-18 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JP4145359B2 (ja) 2008-09-03
DE69824368T2 (de) 2005-06-16
US5966616A (en) 1999-10-12
JP2000511706A (ja) 2000-09-05

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL