DE69823659D1 - Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung - Google Patents

Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung

Info

Publication number
DE69823659D1
DE69823659D1 DE69823659T DE69823659T DE69823659D1 DE 69823659 D1 DE69823659 D1 DE 69823659D1 DE 69823659 T DE69823659 T DE 69823659T DE 69823659 T DE69823659 T DE 69823659T DE 69823659 D1 DE69823659 D1 DE 69823659D1
Authority
DE
Germany
Prior art keywords
arrangement
semiconductor memory
hierarchical cell
cell decoding
circuit arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69823659T
Other languages
English (en)
Inventor
Giovanni Campardo
Rino Micheloni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69823659D1 publication Critical patent/DE69823659D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
DE69823659T 1998-09-30 1998-09-30 Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung Expired - Lifetime DE69823659D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98830570A EP0991075B1 (de) 1998-09-30 1998-09-30 Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung

Publications (1)

Publication Number Publication Date
DE69823659D1 true DE69823659D1 (de) 2004-06-09

Family

ID=8236808

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69823659T Expired - Lifetime DE69823659D1 (de) 1998-09-30 1998-09-30 Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung

Country Status (4)

Country Link
US (1) US6515911B2 (de)
EP (1) EP0991075B1 (de)
JP (1) JP4316743B2 (de)
DE (1) DE69823659D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100655279B1 (ko) * 2000-12-14 2006-12-08 삼성전자주식회사 불휘발성 반도체 메모리 장치
US6829168B2 (en) * 2001-12-28 2004-12-07 Stmicroelectronics S.R.L. Power supply circuit structure for a row decoder of a multilevel non-volatile memory device
US6768683B1 (en) * 2002-03-12 2004-07-27 Advanced Micro Devices, Inc. Low column leakage flash memory array
US6862223B1 (en) * 2002-07-05 2005-03-01 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
JP4721256B2 (ja) 2004-11-17 2011-07-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7369437B2 (en) 2005-12-16 2008-05-06 Sandisk Corporation System for reading non-volatile storage with efficient setup
US7545675B2 (en) 2005-12-16 2009-06-09 Sandisk Corporation Reading non-volatile storage with efficient setup
US7492633B2 (en) 2006-06-19 2009-02-17 Sandisk Corporation System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines
US7349261B2 (en) 2006-06-19 2008-03-25 Sandisk Corporation Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines
US8189396B2 (en) 2006-12-14 2012-05-29 Mosaid Technologies Incorporated Word line driver in a hierarchical NOR flash memory
CN101853700B (zh) * 2007-03-13 2014-11-05 考文森智财管理公司 或非快闪存储器及其字线驱动器电路
DE102010029055B4 (de) * 2010-05-18 2015-11-26 WEGU GmbH Schwingungsdämpfung Drehschwingungstilger für hohe Drehzahlen
US8750049B2 (en) * 2010-06-02 2014-06-10 Stmicroelectronics International N.V. Word line driver for memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3024687B2 (ja) * 1990-06-05 2000-03-21 三菱電機株式会社 半導体記憶装置
JP2835215B2 (ja) 1991-07-25 1998-12-14 株式会社東芝 不揮発性半導体記憶装置
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
KR0164358B1 (ko) * 1995-08-31 1999-02-18 김광호 반도체 메모리 장치의 서브워드라인 디코더
EP0822660A1 (de) * 1996-07-31 1998-02-04 STMicroelectronics S.r.l. Ausgangspufferschaltung mit niedriger Störspannung für elektronische Halbleiterschaltungen
KR100200724B1 (ko) * 1996-08-21 1999-06-15 윤종용 반도체 메모리장치의 서브 워드라인 드라이버
JP3156618B2 (ja) 1997-01-30 2001-04-16 日本電気株式会社 不揮発性半導体記憶装置
JP2964982B2 (ja) 1997-04-01 1999-10-18 日本電気株式会社 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
JP2000113689A (ja) 2000-04-21
JP4316743B2 (ja) 2009-08-19
US20020021584A1 (en) 2002-02-21
US6515911B2 (en) 2003-02-04
EP0991075A1 (de) 2000-04-05
EP0991075B1 (de) 2004-05-06

Similar Documents

Publication Publication Date Title
DE69924916D1 (de) Speicherschaltung
EE200000602A (et) Integraallülitusega varustatud paberist valmistatud põhimik
ATE210838T1 (de) Verbindungsanordnung mit hoher dichte
DE69943120D1 (de) Integrierte Halbleiterschaltung
DE69923244D1 (de) Magnetoresistiven Speicheranordnungen
DE69822280D1 (de) Halbleiterspeicher
DE69832566D1 (de) Halbleiterspeicher mit hierarchischer Bitleitungsstruktur aus nicht-uniformen lokalen Bitleitungen
DE69921737D1 (de) Magnetische Speicherzelle
DE69919045D1 (de) Spannungserhöhungsschaltung für Speicheranordnung
DE69930586D1 (de) Integrierte Halbleiterspeicherschaltung
DE69823659D1 (de) Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung
PT1119430E (pt) Fresa
NO20012196L (no) Offshore senkekasse
DE69907997D1 (de) Halbleiterspeicherschaltung mit Redundanz
DE69832348D1 (de) Speicherschaltung
DE69909280D1 (de) Halbleiterspeicher
DE69819877D1 (de) Elektronisches Mikrometer
DE69627152D1 (de) Leseschaltung für Halbleiter-Speicherzellen
DE59913423D1 (de) Speicherzellenanordnung
DE69907590D1 (de) Halbleitermodul
DE69809096T2 (de) Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher
DE1100202T1 (de) Entschachtelungsschaltung
DE69902712D1 (de) Halbleiterspeicheranordnung
DE69841446D1 (de) Halbleiterspeicher
DE69923900D1 (de) Architektur einer Speicherschaltung

Legal Events

Date Code Title Description
8332 No legal effect for de