DE69821461D1 - Logische Schaltung mit eigener Takterzeugung und zugehöriges Verfahren - Google Patents

Logische Schaltung mit eigener Takterzeugung und zugehöriges Verfahren

Info

Publication number
DE69821461D1
DE69821461D1 DE69821461T DE69821461T DE69821461D1 DE 69821461 D1 DE69821461 D1 DE 69821461D1 DE 69821461 T DE69821461 T DE 69821461T DE 69821461 T DE69821461 T DE 69821461T DE 69821461 D1 DE69821461 D1 DE 69821461D1
Authority
DE
Germany
Prior art keywords
clock generation
logical circuit
associated procedure
procedure
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69821461T
Other languages
English (en)
Other versions
DE69821461T2 (de
Inventor
Richard Relph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69821461D1 publication Critical patent/DE69821461D1/de
Application granted granted Critical
Publication of DE69821461T2 publication Critical patent/DE69821461T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
DE69821461T 1997-12-18 1998-05-21 Logische Schaltung mit eigener Takterzeugung und zugehöriges Verfahren Expired - Lifetime DE69821461T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US992634 1997-12-18
US08/992,634 US6064232A (en) 1997-12-18 1997-12-18 Self-clocked logic circuit and methodology

Publications (2)

Publication Number Publication Date
DE69821461D1 true DE69821461D1 (de) 2004-03-11
DE69821461T2 DE69821461T2 (de) 2004-11-25

Family

ID=25538564

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69821461T Expired - Lifetime DE69821461T2 (de) 1997-12-18 1998-05-21 Logische Schaltung mit eigener Takterzeugung und zugehöriges Verfahren

Country Status (4)

Country Link
US (1) US6064232A (de)
EP (1) EP0924859B1 (de)
JP (1) JPH11185492A (de)
DE (1) DE69821461T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232796B1 (en) * 1999-07-21 2001-05-15 Rambus Incorporated Apparatus and method for detecting two data bits per clock edge
US6369614B1 (en) * 2000-05-25 2002-04-09 Sun Microsystems, Inc. Asynchronous completion prediction
JP2002083000A (ja) * 2000-09-06 2002-03-22 Fujitsu Ltd 論理回路設計方法及び論理回路
US6621302B2 (en) * 2001-03-21 2003-09-16 Bae Systems Information And Electronic Systems Integration, Inc Efficient sequential circuits using critical race control
US6731147B2 (en) 2001-10-29 2004-05-04 Cypress Semiconductor Corp. Method and architecture for self-clocking digital delay locked loop
WO2003071681A1 (en) * 2002-02-21 2003-08-28 Koninklijke Philips Electronics N.V. Integrated circuit having reduced substrate bounce
WO2005048264A1 (en) * 2003-11-12 2005-05-26 Koninklijke Philips Electronics N.V. Controlling power consumption peaks in electronic circuits
DE102005033270B4 (de) * 2005-07-15 2007-11-29 Texas Instruments Deutschland Gmbh Digitale Logikeinheit
US7671579B1 (en) * 2006-03-09 2010-03-02 Altera Corporation Method and apparatus for quantifying and minimizing skew between signals
US8543750B1 (en) 2008-10-15 2013-09-24 Octasic Inc. Method for sharing a resource and circuit making use of same
US8689218B1 (en) * 2008-10-15 2014-04-01 Octasic Inc. Method for sharing a resource and circuit making use of same
US8130019B1 (en) * 2008-10-15 2012-03-06 Octasic Inc. Clock signal propagation method for integrated circuits (ICs) and integrated circuit making use of same
US9602106B1 (en) * 2015-03-05 2017-03-21 Altera Corporation Methods for optimizing circuit performance via configurable clock skews
CN111510137A (zh) * 2020-06-04 2020-08-07 深圳比特微电子科技有限公司 时钟电路、计算芯片、算力板和数字货币挖矿机

Family Cites Families (23)

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Publication number Priority date Publication date Assignee Title
US4929850A (en) * 1987-09-17 1990-05-29 Texas Instruments Incorporated Metastable resistant flip-flop
US5033066A (en) * 1990-02-16 1991-07-16 Hughes Aircraft Company Event tagging time delay
EP0453171A3 (en) * 1990-04-18 1992-11-19 Quickturn Systems Inc Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5111086A (en) * 1990-11-19 1992-05-05 Wang Laboratories, Inc. Adjusting delay circuitry
JPH0528789A (ja) * 1991-07-25 1993-02-05 Sharp Corp 論理回路
US5132572A (en) * 1991-08-12 1992-07-21 Advanced Micro Devices, Inc. High-speed CMOS-to-ECL translator circuit
DE4137340C1 (en) * 1991-11-13 1992-11-26 Siemens Ag, 8000 Muenchen, De Bistable flip=flop circuit comprising two D=flip=flops and correction circuit - checks output level of first flip=flop and uses correction signal to switch through output of flip=flop or reference signal to second flip=flop
US5227679A (en) * 1992-01-02 1993-07-13 Advanced Micro Devices, Inc. Cmos digital-controlled delay gate
US5220216A (en) * 1992-01-02 1993-06-15 Woo Ann K Programmable driving power of a CMOS gate
US5252867A (en) * 1992-02-14 1993-10-12 Vlsi Technology, Inc. Self-compensating digital delay semiconductor device with selectable output delays and method therefor
DE4206082C1 (de) * 1992-02-27 1993-04-08 Siemens Ag, 8000 Muenchen, De
US5229668A (en) * 1992-03-25 1993-07-20 North Carolina State University Of Raleigh Method and apparatus for high speed digital sampling of a data signal
US5363419A (en) * 1992-04-24 1994-11-08 Advanced Micro Devices, Inc. Dual phase-locked-loop having forced mid range fine control zero at handover
US5367542A (en) * 1992-06-19 1994-11-22 Advanced Micro Devices, Inc. Digital data recovery using delay time rulers
US5452333A (en) * 1992-06-19 1995-09-19 Advanced Micro Devices, Inc. Digital jitter correction method and signal preconditioner
US5349612A (en) * 1992-06-19 1994-09-20 Advanced Micro Devices, Inc. Digital serializer and time delay regulator
US5264745A (en) * 1992-08-28 1993-11-23 Advanced Micro Devices, Inc. Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator
US5400370A (en) * 1993-02-24 1995-03-21 Advanced Micro Devices Inc. All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging
US5457719A (en) * 1993-08-11 1995-10-10 Advanced Micro Devices Inc. All digital on-the-fly time delay calibrator
US5457336A (en) * 1994-10-13 1995-10-10 Advanced Micro Devices, Inc. Non-volatile memory structure including protection and structure for maintaining threshold stability
US5565798A (en) * 1995-08-21 1996-10-15 International Business Machines Corporation Self-timed control circuit for self-resetting logic circuitry
GB2310738B (en) * 1996-02-29 2000-02-16 Advanced Risc Mach Ltd Dynamic logic pipeline control
US5764083A (en) * 1996-06-10 1998-06-09 International Business Machines Corporation Pipelined clock distribution for self resetting CMOS circuits

Also Published As

Publication number Publication date
EP0924859B1 (de) 2004-02-04
EP0924859A1 (de) 1999-06-23
DE69821461T2 (de) 2004-11-25
US6064232A (en) 2000-05-16
JPH11185492A (ja) 1999-07-09

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Legal Events

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