DE69802865D1 - Logische Domino-Schaltungen - Google Patents

Logische Domino-Schaltungen

Info

Publication number
DE69802865D1
DE69802865D1 DE69802865T DE69802865T DE69802865D1 DE 69802865 D1 DE69802865 D1 DE 69802865D1 DE 69802865 T DE69802865 T DE 69802865T DE 69802865 T DE69802865 T DE 69802865T DE 69802865 D1 DE69802865 D1 DE 69802865D1
Authority
DE
Germany
Prior art keywords
logical
domino circuits
domino
circuits
logical domino
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69802865T
Other languages
English (en)
Other versions
DE69802865T2 (de
Inventor
Patrick W Bosshart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69802865D1 publication Critical patent/DE69802865D1/de
Application granted granted Critical
Publication of DE69802865T2 publication Critical patent/DE69802865T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE69802865T 1997-05-19 1998-05-14 Logische Domino-Schaltungen Expired - Lifetime DE69802865T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US4702897P 1997-05-19 1997-05-19
US47028P 1997-05-19

Publications (2)

Publication Number Publication Date
DE69802865D1 true DE69802865D1 (de) 2002-01-24
DE69802865T2 DE69802865T2 (de) 2004-03-25

Family

ID=21946689

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69802865T Expired - Lifetime DE69802865T2 (de) 1997-05-19 1998-05-14 Logische Domino-Schaltungen

Country Status (4)

Country Link
US (1) US6040716A (de)
EP (1) EP0880231B1 (de)
JP (1) JP4099261B2 (de)
DE (1) DE69802865T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025225A (en) * 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
KR100314732B1 (ko) * 1998-09-28 2002-01-17 박종섭 논리합회로를이용한상태머신
US6154045A (en) * 1998-12-22 2000-11-28 Intel Corporation Method and apparatus for reducing signal transmission delay using skewed gates
US6265899B1 (en) * 1999-06-04 2001-07-24 S3 Incorporated Single rail domino logic for four-phase clocking scheme
US6242952B1 (en) * 1999-09-24 2001-06-05 Texas Instruments Incorporated Inverting hold time latch circuits, systems, and methods
US6737888B1 (en) * 1999-11-08 2004-05-18 International Business Machines Corporation Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement
US6836755B2 (en) * 1999-12-30 2004-12-28 Intel Corporation Method and apparatus for fully automated signal integrity analysis for domino circuitry
US6462581B1 (en) * 2000-04-03 2002-10-08 International Business Machines Corporation Programmable timing boundary in dynamic circuits
US6549040B1 (en) * 2000-06-29 2003-04-15 Intel Corporation Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates
US6531897B1 (en) 2000-06-30 2003-03-11 Intel Corporation Global clock self-timed circuit with self-terminating precharge for high frequency applications
US6542006B1 (en) * 2000-06-30 2003-04-01 Intel Corporation Reset first latching mechanism for pulsed circuit topologies
US6496038B1 (en) 2000-06-30 2002-12-17 Intel Corporation Pulsed circuit topology including a pulsed, domino flip-flop
US6567337B1 (en) 2000-06-30 2003-05-20 Intel Corporation Pulsed circuit topology to perform a memory array write operation
US6420904B1 (en) * 2001-01-25 2002-07-16 Koninklijke Philips Electronics N.V. Domino logic with self-timed precharge
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US6977528B2 (en) * 2002-09-03 2005-12-20 The Regents Of The University Of California Event driven dynamic logic for reducing power consumption
US6978387B2 (en) * 2002-11-29 2005-12-20 Texas Instruments Incorporated Hold time latch with decreased percharge node voltage leakage
US7429880B2 (en) * 2003-08-11 2008-09-30 Amar Pal Singh Rana Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
US7098695B2 (en) * 2004-06-30 2006-08-29 Qualcomm Incorporated Dynamic-to-static logic converter
KR100684871B1 (ko) 2004-07-02 2007-02-20 삼성전자주식회사 저전력 파이프라인 도미노 로직
US7233639B2 (en) * 2004-12-17 2007-06-19 Stmicroelectronics, Inc. Unfooted domino logic circuit and method
JP4645238B2 (ja) 2005-03-09 2011-03-09 日本電気株式会社 半導体装置
US7282960B2 (en) * 2005-06-28 2007-10-16 International Business Machines Corporation Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
JP4791195B2 (ja) * 2006-01-30 2011-10-12 パナソニック株式会社 ダイナミック回路
US20090167395A1 (en) * 2007-12-31 2009-07-02 Texas Instruments Incorporated High performance latches
US7683688B2 (en) * 2007-12-31 2010-03-23 Texas Instruments Incorporated High performance clocked latches and devices therefrom
KR101911060B1 (ko) * 2012-03-19 2018-10-23 삼성전자주식회사 푸터가 없는 ｎｐ 도미노 로직 회로와 이를 포함하는 장치들
US8493093B1 (en) * 2012-06-12 2013-07-23 International Business Machines Corporation Time division multiplexed limited switch dynamic logic
CN108832922B (zh) * 2018-06-25 2022-03-22 温州大学 一种基于虚拟孔的多米诺混淆电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121003A (en) * 1990-10-10 1992-06-09 Hal Computer Systems, Inc. Zero overhead self-timed iterative logic
JP3467286B2 (ja) * 1992-05-19 2003-11-17 ヒューレット・パッカード・カンパニー 論理評価システム
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output

Also Published As

Publication number Publication date
EP0880231B1 (de) 2001-12-12
DE69802865T2 (de) 2004-03-25
JP4099261B2 (ja) 2008-06-11
US6040716A (en) 2000-03-21
JPH10336015A (ja) 1998-12-18
EP0880231A1 (de) 1998-11-25

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Legal Events

Date Code Title Description
8332 No legal effect for de
8328 Change in the person/name/address of the agent

Free format text: PRINZ UND PARTNER GBR, 81241 MUENCHEN

8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition