DE69817713D1 - Verfahren und System zum Erzeugen eines Prozessortaktes mit schnellem Startvorgang - Google Patents

Verfahren und System zum Erzeugen eines Prozessortaktes mit schnellem Startvorgang

Info

Publication number
DE69817713D1
DE69817713D1 DE69817713T DE69817713T DE69817713D1 DE 69817713 D1 DE69817713 D1 DE 69817713D1 DE 69817713 T DE69817713 T DE 69817713T DE 69817713 T DE69817713 T DE 69817713T DE 69817713 D1 DE69817713 D1 DE 69817713D1
Authority
DE
Germany
Prior art keywords
generating
processor clock
fast start
fast
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69817713T
Other languages
English (en)
Other versions
DE69817713T2 (de
Inventor
Jeffrey R Hardesty
Geoffrey Hall
Kelvin Mccollough
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69817713D1 publication Critical patent/DE69817713D1/de
Application granted granted Critical
Publication of DE69817713T2 publication Critical patent/DE69817713T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Power Sources (AREA)
DE69817713T 1997-07-28 1998-07-13 Verfahren und System zum Erzeugen eines Prozessortaktes mit schnellem Startvorgang Expired - Fee Related DE69817713T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/901,645 US5963068A (en) 1997-07-28 1997-07-28 Fast start-up processor clock generation method and system
US901645 1997-07-28

Publications (2)

Publication Number Publication Date
DE69817713D1 true DE69817713D1 (de) 2003-10-09
DE69817713T2 DE69817713T2 (de) 2004-04-08

Family

ID=25414580

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69817713T Expired - Fee Related DE69817713T2 (de) 1997-07-28 1998-07-13 Verfahren und System zum Erzeugen eines Prozessortaktes mit schnellem Startvorgang

Country Status (6)

Country Link
US (1) US5963068A (de)
EP (1) EP0895358B1 (de)
JP (1) JP4206151B2 (de)
KR (1) KR100546227B1 (de)
DE (1) DE69817713T2 (de)
TW (1) TW445404B (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005904A (en) * 1997-10-16 1999-12-21 Oasis Design, Inc. Phase-locked loop with protected output during instances when the phase-locked loop is unlocked
US6763060B1 (en) * 1999-02-19 2004-07-13 Oasis Silicon Systems Communication system employing a network of power managed transceivers that can generate a clocking signal or enable data bypass of a digital system associated with each transceiver
JP2000305655A (ja) * 1999-04-19 2000-11-02 Mitsubishi Electric Corp 周波数逓倍回路内蔵のマイクロコンピュータ
JP4020548B2 (ja) * 1999-11-11 2007-12-12 富士通株式会社 フリップフロップ制御回路、プロセッサおよびプロセッサの動作方法
US6859509B1 (en) * 2000-02-04 2005-02-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Wide bandwidth phase-locked loop circuit
KR100507880B1 (ko) * 2000-05-31 2005-08-17 매그나칩 반도체 유한회사 개선된 위상고정루프 회로
EP1289150A1 (de) * 2001-08-24 2003-03-05 STMicroelectronics S.r.l. Verfahren zum Erzeugen eines Signals veränderbarer Frequenz, zum Beispiel zum Spreizen des Sprektrums eines Taktsignals, und Vorrichtung dafür
US6889331B2 (en) 2001-08-29 2005-05-03 Analog Devices, Inc. Dynamic voltage control method and apparatus
TW565758B (en) * 2001-09-19 2003-12-11 Alps Electric Co Ltd Computer suppressing of unnecessary signals
US7036032B2 (en) * 2002-01-04 2006-04-25 Ati Technologies, Inc. System for reduced power consumption by phase locked loop and method thereof
US7370189B2 (en) * 2004-09-30 2008-05-06 Intel Corporation Method and apparatus for establishing safe processor operating points in connection with a secure boot
GB2450564B (en) * 2007-06-29 2011-03-02 Imagination Tech Ltd Clock frequency adjustment for semi-conductor devices
US9041452B2 (en) * 2010-01-27 2015-05-26 Silicon Laboratories Inc. Circuit and method of clocking multiple digital circuits in multiple phases
JP2014090344A (ja) 2012-10-31 2014-05-15 Nec Corp クロック信号初期化回路およびその方法
JP6466740B2 (ja) * 2015-03-02 2019-02-06 株式会社メガチップス クロック生成回路
KR102298160B1 (ko) * 2015-08-13 2021-09-03 삼성전자주식회사 반도체 장치 및 이를 포함하는 통신 시스템
KR102092126B1 (ko) 2018-11-20 2020-03-23 배운성 이물질 감김 방지용 보트 스크류 보호장치
FR3098665B1 (fr) * 2019-07-09 2021-07-30 St Microelectronics Rousset Procédé de gestion du démarrage d’une boucle à verrouillage de phase, et circuit intégré correspondant
CN113839666A (zh) * 2020-06-24 2021-12-24 意法半导体(鲁塞)公司 用于管理锁相环的启动的处理和对应的集成电路
FR3112044B1 (fr) * 2020-06-24 2023-10-27 St Microelectronics Rousset Procédé de gestion du démarrage d’une boucle à verrouillage de phase, et circuit intégré correspondant
US12040804B2 (en) * 2022-04-28 2024-07-16 Parade Technologies, Ltd. Methods and systems for controlling frequency variation for a PLL reference clock

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748559A (en) * 1979-08-09 1988-05-31 Motorola, Inc. Apparatus for reducing power consumed by a static microprocessor
US4758945A (en) * 1979-08-09 1988-07-19 Motorola, Inc. Method for reducing power consumed by a static microprocessor
US4893271A (en) * 1983-11-07 1990-01-09 Motorola, Inc. Synthesized clock microcomputer with power saving
GB2228598A (en) * 1989-02-28 1990-08-29 Ibm Clock signal generator for a data processing system
JPH06253568A (ja) * 1993-03-03 1994-09-09 Sony Corp 基準信号発生装置
US5579353A (en) * 1993-10-12 1996-11-26 Texas Instruments Incorporated Dynamic clock mode switch
JPH08166834A (ja) * 1994-12-14 1996-06-25 Mitsubishi Electric Corp クロック発生回路及びマイクロコンピュータ
US5694308A (en) * 1995-07-03 1997-12-02 Motorola, Inc. Method and apparatus for regulated low voltage charge pump
US5774701A (en) * 1995-07-10 1998-06-30 Hitachi, Ltd. Microprocessor operating at high and low clok frequencies
JPH0993126A (ja) * 1995-09-28 1997-04-04 Nec Corp クロック発生器
US5623234A (en) * 1996-03-04 1997-04-22 Motorola Clock system

Also Published As

Publication number Publication date
JP4206151B2 (ja) 2009-01-07
JPH11234125A (ja) 1999-08-27
KR19990014219A (ko) 1999-02-25
EP0895358A3 (de) 1999-04-14
EP0895358A2 (de) 1999-02-03
EP0895358B1 (de) 2003-09-03
US5963068A (en) 1999-10-05
DE69817713T2 (de) 2004-04-08
KR100546227B1 (ko) 2006-03-28
TW445404B (en) 2001-07-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee