DE69814590D1 - Leistungsfreier hochgeschwindigkeitskonfigurationsspeicher - Google Patents

Leistungsfreier hochgeschwindigkeitskonfigurationsspeicher

Info

Publication number
DE69814590D1
DE69814590D1 DE69814590T DE69814590T DE69814590D1 DE 69814590 D1 DE69814590 D1 DE 69814590D1 DE 69814590 T DE69814590 T DE 69814590T DE 69814590 T DE69814590 T DE 69814590T DE 69814590 D1 DE69814590 D1 DE 69814590D1
Authority
DE
Germany
Prior art keywords
configuration memory
performance high
speed configuration
speed
performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69814590T
Other languages
English (en)
Other versions
DE69814590T2 (de
Inventor
Saroj Pathak
A Rosendale
E Payne
Nianglamching Hangzo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of DE69814590D1 publication Critical patent/DE69814590D1/de
Publication of DE69814590T2 publication Critical patent/DE69814590T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69814590T 1997-11-25 1998-11-19 Leistungsfreier hochgeschwindigkeitskonfigurationsspeicher Expired - Lifetime DE69814590T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US978286 1992-11-18
US08/978,286 US5946267A (en) 1997-11-25 1997-11-25 Zero power high speed configuration memory
PCT/US1998/025003 WO1999027538A1 (en) 1997-11-25 1998-11-19 Zero power high speed configuration memory

Publications (2)

Publication Number Publication Date
DE69814590D1 true DE69814590D1 (de) 2003-06-18
DE69814590T2 DE69814590T2 (de) 2004-03-18

Family

ID=25525944

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69814590T Expired - Lifetime DE69814590T2 (de) 1997-11-25 1998-11-19 Leistungsfreier hochgeschwindigkeitskonfigurationsspeicher

Country Status (12)

Country Link
US (1) US5946267A (de)
EP (1) EP0954864B1 (de)
JP (1) JP2001511286A (de)
KR (1) KR20000070410A (de)
CN (1) CN1180435C (de)
CA (1) CA2278615A1 (de)
DE (1) DE69814590T2 (de)
HK (1) HK1023211A1 (de)
MY (1) MY114495A (de)
NO (1) NO993614L (de)
TW (1) TW430817B (de)
WO (1) WO1999027538A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6651199B1 (en) * 2000-06-22 2003-11-18 Xilinx, Inc. In-system programmable flash memory device with trigger circuit for generating limited duration program instruction
US6839873B1 (en) * 2000-06-23 2005-01-04 Cypress Semiconductor Corporation Method and apparatus for programmable logic device (PLD) built-in-self-test (BIST)
US6744291B2 (en) 2002-08-30 2004-06-01 Atmel Corporation Power-on reset circuit
JP4747023B2 (ja) * 2006-04-27 2011-08-10 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US8711639B2 (en) 2010-11-02 2014-04-29 Micron Technology, Inc. Data paths using a first signal to capture data and a second signal to output data and methods for providing data
US9910473B2 (en) 2013-03-14 2018-03-06 Silicon Storage Technology, Inc. Power management for a memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330852A (en) * 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
US5042014A (en) * 1987-05-21 1991-08-20 Texas Instruments Incorporated Dual-port memory having pipelined serial output
US5086388A (en) * 1988-03-18 1992-02-04 Hitachi Maxell, Ltd. Semiconductor serial/parallel-parallel/serial file memory and storage system
JPH02201797A (ja) * 1989-01-31 1990-08-09 Toshiba Corp 半導体メモリ装置
JPH06275069A (ja) * 1993-03-20 1994-09-30 Hitachi Ltd シリアルメモリ
JP3351692B2 (ja) * 1995-09-12 2002-12-03 株式会社東芝 シンクロナス半導体メモリ装置
US5748559A (en) * 1996-01-17 1998-05-05 Cypress Semiconductor Corporation Circuit for high speed serial programming of programmable logic devices

Also Published As

Publication number Publication date
CA2278615A1 (en) 1999-06-03
HK1023211A1 (en) 2000-09-01
DE69814590T2 (de) 2004-03-18
EP0954864A4 (de) 2001-01-31
TW430817B (en) 2001-04-21
MY114495A (en) 2002-10-31
WO1999027538A1 (en) 1999-06-03
NO993614L (no) 1999-09-27
US5946267A (en) 1999-08-31
CN1244280A (zh) 2000-02-09
NO993614D0 (no) 1999-07-26
EP0954864B1 (de) 2003-05-14
EP0954864A1 (de) 1999-11-10
KR20000070410A (ko) 2000-11-25
JP2001511286A (ja) 2001-08-07
CN1180435C (zh) 2004-12-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition