DE69809012D1 - Reduktion der Erosion von Maskenschichten - Google Patents

Reduktion der Erosion von Maskenschichten

Info

Publication number
DE69809012D1
DE69809012D1 DE69809012T DE69809012T DE69809012D1 DE 69809012 D1 DE69809012 D1 DE 69809012D1 DE 69809012 T DE69809012 T DE 69809012T DE 69809012 T DE69809012 T DE 69809012T DE 69809012 D1 DE69809012 D1 DE 69809012D1
Authority
DE
Germany
Prior art keywords
erosion
reduction
mask layers
mask
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69809012T
Other languages
English (en)
Other versions
DE69809012T2 (de
Inventor
Robert Ploessl
Bertrand Flienter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE69809012D1 publication Critical patent/DE69809012D1/de
Publication of DE69809012T2 publication Critical patent/DE69809012T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)
DE69809012T 1997-09-30 1998-08-20 Reduktion der Erosion von Maskenschichten Expired - Lifetime DE69809012T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US940233 1997-09-30
US08/940,233 US5907771A (en) 1997-09-30 1997-09-30 Reduction of pad erosion

Publications (2)

Publication Number Publication Date
DE69809012D1 true DE69809012D1 (de) 2002-12-05
DE69809012T2 DE69809012T2 (de) 2004-02-26

Family

ID=25474462

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69809012T Expired - Lifetime DE69809012T2 (de) 1997-09-30 1998-08-20 Reduktion der Erosion von Maskenschichten

Country Status (7)

Country Link
US (1) US5907771A (de)
EP (1) EP0905749B1 (de)
JP (1) JPH11177064A (de)
KR (1) KR100504262B1 (de)
CN (1) CN1134838C (de)
DE (1) DE69809012T2 (de)
TW (1) TW426949B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190955B1 (en) * 1998-01-27 2001-02-20 International Business Machines Corporation Fabrication of trench capacitors using disposable hard mask
US6440858B1 (en) * 1998-08-24 2002-08-27 International Business Machines Corporation Multi-layer hard mask for deep trench silicon etch
US6734108B1 (en) * 1999-09-27 2004-05-11 Cypress Semiconductor Corporation Semiconductor structure and method of making contacts in a semiconductor structure
US20060261436A1 (en) * 2005-05-19 2006-11-23 Freescale Semiconductor, Inc. Electronic device including a trench field isolation region and a process for forming the same
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US20070249127A1 (en) * 2006-04-24 2007-10-25 Freescale Semiconductor, Inc. Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same
US7491622B2 (en) * 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
US7528078B2 (en) 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
KR101075490B1 (ko) * 2009-01-30 2011-10-21 주식회사 하이닉스반도체 매립게이트를 구비한 반도체장치 및 그 제조 방법
KR20140145419A (ko) * 2013-06-13 2014-12-23 삼성전자주식회사 반도체 소자 제조 방법
CN105609503A (zh) * 2016-01-25 2016-05-25 中国科学院微电子研究所 存储单元、存储器件及电子设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939104A (en) * 1984-10-31 1990-07-03 Texas Instruments, Incorporated Method for forming a buried lateral contact
US5118384A (en) * 1990-04-03 1992-06-02 International Business Machines Corporation Reactive ion etching buffer mask
JPH05110017A (ja) * 1991-10-18 1993-04-30 Hitachi Ltd 半導体装置とその製造方法
JP3439493B2 (ja) * 1992-12-01 2003-08-25 沖電気工業株式会社 半導体記憶装置の製造方法
DE19600423C2 (de) * 1996-01-08 2001-07-05 Siemens Ag Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5686345A (en) * 1996-01-30 1997-11-11 International Business Machines Corporation Trench mask for forming deep trenches in a semiconductor substrate, and method of using same
US5776808A (en) * 1996-12-26 1998-07-07 Siemens Aktiengesellschaft Pad stack with a poly SI etch stop for TEOS mask removal with RIE

Also Published As

Publication number Publication date
KR19990030229A (ko) 1999-04-26
KR100504262B1 (ko) 2005-09-26
EP0905749A3 (de) 2000-01-12
EP0905749A2 (de) 1999-03-31
TW426949B (en) 2001-03-21
JPH11177064A (ja) 1999-07-02
EP0905749B1 (de) 2002-10-30
DE69809012T2 (de) 2004-02-26
CN1134838C (zh) 2004-01-14
CN1213171A (zh) 1999-04-07
US5907771A (en) 1999-05-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE

8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE