DE69800721D1 - Verfahren zur Reinigung von halbleitenden Substraten nach dem Läppen - Google Patents

Verfahren zur Reinigung von halbleitenden Substraten nach dem Läppen

Info

Publication number
DE69800721D1
DE69800721D1 DE69800721T DE69800721T DE69800721D1 DE 69800721 D1 DE69800721 D1 DE 69800721D1 DE 69800721 T DE69800721 T DE 69800721T DE 69800721 T DE69800721 T DE 69800721T DE 69800721 D1 DE69800721 D1 DE 69800721D1
Authority
DE
Germany
Prior art keywords
lapping
cleaning
semiconducting substrates
semiconducting
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69800721T
Other languages
English (en)
Other versions
DE69800721T2 (de
Inventor
Seiichi Miyazaki
Sumiyoshi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69800721D1 publication Critical patent/DE69800721D1/de
Application granted granted Critical
Publication of DE69800721T2 publication Critical patent/DE69800721T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Cleaning And De-Greasing Of Metallic Materials By Chemical Methods (AREA)
  • ing And Chemical Polishing (AREA)
  • Cleaning By Liquid Or Steam (AREA)
  • Grinding-Machine Dressing And Accessory Apparatuses (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
DE69800721T 1997-02-21 1998-02-11 Verfahren zur Reinigung von halbleitenden Substraten nach dem Läppen Expired - Lifetime DE69800721T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05409997A JP3305610B2 (ja) 1997-02-21 1997-02-21 ラッピング後の半導体ウエーハの洗浄方法

Publications (2)

Publication Number Publication Date
DE69800721D1 true DE69800721D1 (de) 2001-05-31
DE69800721T2 DE69800721T2 (de) 2001-11-22

Family

ID=12961183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69800721T Expired - Lifetime DE69800721T2 (de) 1997-02-21 1998-02-11 Verfahren zur Reinigung von halbleitenden Substraten nach dem Läppen

Country Status (6)

Country Link
US (1) US5976983A (de)
EP (1) EP0860864B1 (de)
JP (1) JP3305610B2 (de)
DE (1) DE69800721T2 (de)
MY (1) MY118821A (de)
TW (1) TW513329B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11135474A (ja) * 1997-10-30 1999-05-21 Komatsu Electron Metals Co Ltd 半導体鏡面ウェハおよびその製造方法
EP1564796A1 (de) * 1997-12-09 2005-08-17 Shin-Etsu Handotai Company Limited Herstellungsverfahren für Halbleiterscheiben und danach hergestellte Halbleiterscheiben
US6099662A (en) * 1999-02-11 2000-08-08 Taiwan Semiconductor Manufacturing Company Process for cleaning a semiconductor substrate after chemical-mechanical polishing
KR100701825B1 (ko) * 1999-04-20 2007-03-30 신에쯔 한도타이 가부시키가이샤 실리콘 에피택셜 웨이퍼 및 그 제조방법
US6632277B2 (en) 1999-07-14 2003-10-14 Seh America, Inc. Optimized silicon wafer gettering for advanced semiconductor devices
US6395085B2 (en) 1999-07-14 2002-05-28 Seh America, Inc. Purity silicon wafer for use in advanced semiconductor devices
US6454852B2 (en) 1999-07-14 2002-09-24 Seh America, Inc. High efficiency silicon wafer optimized for advanced semiconductor devices
KR100701342B1 (ko) * 1999-07-15 2007-03-29 신에쯔 한도타이 가부시키가이샤 접합 웨이퍼의 제조방법 및 접합 웨이퍼
WO2004027840A2 (en) * 2002-09-18 2004-04-01 Memc Electronic Materials, Inc. Process for etching silicon wafers
JP4565994B2 (ja) * 2004-12-28 2010-10-20 信越半導体株式会社 レーザーマーク付き半導体ウェーハの製造方法、及びその半導体ウェーハ
JP4854004B2 (ja) * 2006-02-23 2012-01-11 株式会社テクニスコ 治具の製造方法
JP2009272380A (ja) * 2008-05-01 2009-11-19 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物結晶およびその表面処理方法、ｉｉｉ族窒化物積層体およびその製造方法、ならびにｉｉｉ族窒化物半導体デバイスおよびその製造方法
JP5471001B2 (ja) * 2009-04-20 2014-04-16 住友電気工業株式会社 インジウムリン基板の製造方法、エピタキシャルウエハの製造方法、インジウムリン基板およびエピタキシャルウエハ
JP5216749B2 (ja) * 2009-11-02 2013-06-19 ジルトロニック アクチエンゲゼルシャフト シリコンウエーハの加工方法
JP5668769B2 (ja) * 2013-03-08 2015-02-12 住友電気工業株式会社 Ｉｉｉ族窒化物結晶およびその表面処理方法、ｉｉｉ族窒化物積層体およびその製造方法、ならびにｉｉｉ族窒化物半導体デバイスおよびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918030A (en) * 1989-03-31 1990-04-17 Electric Power Research Institute Method of forming light-trapping surface for photovoltaic cell and resulting structure
US5360509A (en) * 1993-03-08 1994-11-01 Gi Corporation Low cost method of fabricating epitaxial semiconductor devices
JP2910507B2 (ja) * 1993-06-08 1999-06-23 信越半導体株式会社 半導体ウエーハの製造方法

Also Published As

Publication number Publication date
EP0860864A2 (de) 1998-08-26
DE69800721T2 (de) 2001-11-22
EP0860864B1 (de) 2001-04-25
JPH10242087A (ja) 1998-09-11
TW513329B (en) 2002-12-11
JP3305610B2 (ja) 2002-07-24
MY118821A (en) 2005-01-31
US5976983A (en) 1999-11-02
EP0860864A3 (de) 1998-09-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition