DE69718710T2 - Busbrückenanordnung - Google Patents

Busbrückenanordnung

Info

Publication number
DE69718710T2
DE69718710T2 DE69718710T DE69718710T DE69718710T2 DE 69718710 T2 DE69718710 T2 DE 69718710T2 DE 69718710 T DE69718710 T DE 69718710T DE 69718710 T DE69718710 T DE 69718710T DE 69718710 T2 DE69718710 T2 DE 69718710T2
Authority
DE
Germany
Prior art keywords
bus bridge
bridge
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69718710T
Other languages
English (en)
Other versions
DE69718710D1 (de
Inventor
Hideaki Harumoto
Toshiyuki Ochiai
Taihei Yugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69718710D1 publication Critical patent/DE69718710D1/de
Application granted granted Critical
Publication of DE69718710T2 publication Critical patent/DE69718710T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
DE69718710T 1996-06-18 1997-06-17 Busbrückenanordnung Expired - Fee Related DE69718710T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8156781A JPH103447A (ja) 1996-06-18 1996-06-18 バスブリッジ装置

Publications (2)

Publication Number Publication Date
DE69718710D1 DE69718710D1 (de) 2003-03-06
DE69718710T2 true DE69718710T2 (de) 2003-10-23

Family

ID=15635179

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69718710T Expired - Fee Related DE69718710T2 (de) 1996-06-18 1997-06-17 Busbrückenanordnung

Country Status (4)

Country Link
US (1) US5978879A (de)
EP (1) EP0814408B1 (de)
JP (1) JPH103447A (de)
DE (1) DE69718710T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260093B1 (en) 1998-03-31 2001-07-10 Lsi Logic Corporation Method and apparatus for arbitrating access to multiple buses in a data processing system
US6223237B1 (en) * 1998-07-07 2001-04-24 Adaptive Systems, Inc. Expandable communications bus
US6636927B1 (en) * 1999-09-24 2003-10-21 Adaptec, Inc. Bridge device for transferring data using master-specific prefetch sizes
DE10019239B4 (de) * 2000-04-18 2008-09-04 Fujitsu Siemens Computers Gmbh Datenverarbeitungseinrichtung mit einer Schaltungsanordnung zur Verbindung eines ersten Kommunikationsbusses mit einem zweiten Kommunikationsbus
US6775732B2 (en) 2000-09-08 2004-08-10 Texas Instruments Incorporated Multiple transaction bus system
US6976108B2 (en) * 2001-01-31 2005-12-13 Samsung Electronics Co., Ltd. System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities
TW514791B (en) * 2001-05-28 2002-12-21 Via Tech Inc Structure, method and related control chip for accessing device of computer system with system management bus
FI20011257A0 (fi) * 2001-06-13 2001-06-13 Nokia Corp Menetelmä väylän mukauttamiseksi ja väylä
KR101034494B1 (ko) * 2004-02-11 2011-05-17 삼성전자주식회사 개방형 코어 프로토콜을 기반으로 하는 버스 시스템
JP2005250683A (ja) * 2004-03-02 2005-09-15 Renesas Technology Corp マイクロコンピュータ
JP2005346513A (ja) * 2004-06-04 2005-12-15 Renesas Technology Corp 半導体装置
JP4260720B2 (ja) * 2004-10-27 2009-04-30 日本テキサス・インスツルメンツ株式会社 バス制御装置
KR100631202B1 (ko) * 2005-01-11 2006-10-04 삼성전자주식회사 Ｃｄｍａ 버스를 이용한 원칩 시스템 및 그의 데이터전송방법
US7634611B2 (en) * 2006-03-17 2009-12-15 Agilent Technologies, Inc. Multi-master, chained two-wire serial bus
EP2063542B1 (de) * 2006-06-16 2013-06-12 Sharp Kabushiki Kaisha Datenerzeugungsvorrichtung, Datenerzeugungsverfahren, Basisstation, Mobilstation, Synchronisationserkennungsverfahren, Sektoridentifizierungsverfahren, Informationserkennungsverfahren und mobiles Kommunikationssystem
JP2008118211A (ja) * 2006-10-31 2008-05-22 Toshiba Corp データ転送装置及びデータ転送方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257099A (en) * 1975-10-14 1981-03-17 Texas Instruments Incorporated Communication bus coupler
JPH02178753A (ja) * 1988-12-29 1990-07-11 Nissin Electric Co Ltd システムバスのエクステンダ
JPH02178752A (ja) * 1988-12-29 1990-07-11 Nissin Electric Co Ltd システムバスのエクステンダ
US5717873A (en) * 1993-09-30 1998-02-10 Intel Corporation Deadlock avoidance mechanism and method for multiple bus topology
CA2160499A1 (en) * 1994-11-30 1996-05-31 Patrick Maurice Bland Bridge between buses in a system having a plurality of buses with different memory addressing capacities and having an arrangement for reallocating memory segments within the system memory map

Also Published As

Publication number Publication date
EP0814408A2 (de) 1997-12-29
EP0814408B1 (de) 2003-01-29
US5978879A (en) 1999-11-02
EP0814408A3 (de) 2002-03-27
JPH103447A (ja) 1998-01-06
DE69718710D1 (de) 2003-03-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee