DE69710165T2 - Phasenregelschleife - Google Patents

Phasenregelschleife

Info

Publication number
DE69710165T2
DE69710165T2 DE69710165T DE69710165T DE69710165T2 DE 69710165 T2 DE69710165 T2 DE 69710165T2 DE 69710165 T DE69710165 T DE 69710165T DE 69710165 T DE69710165 T DE 69710165T DE 69710165 T2 DE69710165 T2 DE 69710165T2
Authority
DE
Germany
Prior art keywords
phase
locked loop
locked
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69710165T
Other languages
English (en)
Other versions
DE69710165D1 (de
Inventor
Mitsuo Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69710165D1 publication Critical patent/DE69710165D1/de
Publication of DE69710165T2 publication Critical patent/DE69710165T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
DE69710165T 1996-12-05 1997-12-04 Phasenregelschleife Expired - Fee Related DE69710165T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8324920A JP2947192B2 (ja) 1996-12-05 1996-12-05 Pll回路

Publications (2)

Publication Number Publication Date
DE69710165D1 DE69710165D1 (de) 2002-03-14
DE69710165T2 true DE69710165T2 (de) 2002-07-18

Family

ID=18171094

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69710165T Expired - Fee Related DE69710165T2 (de) 1996-12-05 1997-12-04 Phasenregelschleife

Country Status (4)

Country Link
US (1) US5877658A (de)
EP (1) EP0847142B1 (de)
JP (1) JP2947192B2 (de)
DE (1) DE69710165T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2330736B (en) * 1997-10-24 2002-04-10 Mitel Corp Timing recovery with minimum jitter movement
EP1032133A1 (de) * 1999-02-23 2000-08-30 Siemens Aktiengesellschaft Phasenregelkreis mit geringem Phasenfehler
US6160432A (en) * 1999-04-30 2000-12-12 Conexant Systems, Inc. Source-switched or gate-switched charge pump having cascoded output
WO2002061946A1 (en) * 2001-01-26 2002-08-08 True Circuits, Inc. Phase-locked with composite feedback signal formed from phased-shifted variants of output signal
US6873213B2 (en) 2001-10-02 2005-03-29 Nec Compound Semiconductor Devices, Ltd. Fractional N frequency synthesizer
US7092475B1 (en) * 2002-09-25 2006-08-15 National Semiconductor Corporation Phase-frequency detector with linear phase error gain near and during phase-lock in delta sigma phase-locked loop
JP4063779B2 (ja) * 2004-02-27 2008-03-19 三洋電機株式会社 Pll回路
JP2008028683A (ja) * 2006-07-20 2008-02-07 Fujitsu Ltd 位相同期発振器
US7664196B2 (en) 2006-11-08 2010-02-16 Raytheon Company Frequency agile phase locked loop
WO2008116517A1 (de) * 2007-03-26 2008-10-02 Keymile Gmbh Verfahren zur erzeugung einer taktfrequenz
US8773181B2 (en) * 2012-11-30 2014-07-08 Cambridge Silicon Radio, Ltd. Locked loop circuits and methods
CN110336514B (zh) * 2019-07-16 2023-03-14 拉苏尔·阿齐兹潘纳·阿巴果伊 用于一次调频的感应电动机变频驱动系统、方法及应用

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4023116A (en) * 1976-07-08 1977-05-10 Fairchild Camera And Instrument Corporation Phase-locked loop frequency synthesizer
JPS6223620A (ja) * 1985-07-24 1987-01-31 Hitachi Ltd Pll回路
JPS6276324A (ja) * 1985-09-27 1987-04-08 Japan Radio Co Ltd 周波数シンセサイザ
JPH06216767A (ja) * 1992-11-18 1994-08-05 Philips Electron Nv 安定化位相弁別器を備えるフェーズロックドループ用回路
US5699387A (en) * 1993-06-23 1997-12-16 Ati Technologies Inc. Phase offset cancellation technique for reducing low frequency jitters
WO1995034127A1 (en) * 1994-06-03 1995-12-14 Sierra Semiconductor Corporation A three-state phase-detector/charge pump circuit with no dead-band region
JPH08213905A (ja) * 1995-02-08 1996-08-20 Hitachi Ltd 位相同期回路及びそれを用いた周波数シンセサイザ

Also Published As

Publication number Publication date
JPH10163860A (ja) 1998-06-19
EP0847142A1 (de) 1998-06-10
EP0847142B1 (de) 2002-01-30
US5877658A (en) 1999-03-02
JP2947192B2 (ja) 1999-09-13
DE69710165D1 (de) 2002-03-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee