DE69709870T2 - Verwendung einer ätzstopschicht in einer integrierten schaltung für die herstellung von versetzt angeordneten leiterbahnen - Google Patents

Verwendung einer ätzstopschicht in einer integrierten schaltung für die herstellung von versetzt angeordneten leiterbahnen

Info

Publication number
DE69709870T2
DE69709870T2 DE69709870T DE69709870T DE69709870T2 DE 69709870 T2 DE69709870 T2 DE 69709870T2 DE 69709870 T DE69709870 T DE 69709870T DE 69709870 T DE69709870 T DE 69709870T DE 69709870 T2 DE69709870 T2 DE 69709870T2
Authority
DE
Germany
Prior art keywords
dielectric
conductor
conductors
line
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69709870T
Other languages
German (de)
English (en)
Other versions
DE69709870D1 (de
Inventor
Basab Bandyopadhyay
S. Brennan
Robert Dawson
Jim Fulford
N. Hause
W. Michael
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69709870D1 publication Critical patent/DE69709870D1/de
Application granted granted Critical
Publication of DE69709870T2 publication Critical patent/DE69709870T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H10W20/421—Skip vias, i.e. vias that do not connect all metallization layers that they pass through

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69709870T 1996-07-18 1997-05-27 Verwendung einer ätzstopschicht in einer integrierten schaltung für die herstellung von versetzt angeordneten leiterbahnen Expired - Lifetime DE69709870T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68317696A 1996-07-18 1996-07-18
PCT/US1997/009452 WO1998003994A1 (en) 1996-07-18 1997-05-27 Integrated circuit which uses an etch stop for producing staggered interconnect lines

Publications (2)

Publication Number Publication Date
DE69709870D1 DE69709870D1 (de) 2002-02-28
DE69709870T2 true DE69709870T2 (de) 2002-08-22

Family

ID=24742872

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69709870T Expired - Lifetime DE69709870T2 (de) 1996-07-18 1997-05-27 Verwendung einer ätzstopschicht in einer integrierten schaltung für die herstellung von versetzt angeordneten leiterbahnen

Country Status (6)

Country Link
US (1) US5827776A (https=)
EP (1) EP0912996B1 (https=)
JP (1) JP2000515323A (https=)
KR (1) KR100442407B1 (https=)
DE (1) DE69709870T2 (https=)
WO (1) WO1998003994A1 (https=)

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US5847462A (en) * 1996-11-14 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
US6020258A (en) * 1997-07-07 2000-02-01 Yew; Tri-Rung Method for unlanded via etching using etch stop
US6143640A (en) * 1997-09-23 2000-11-07 International Business Machines Corporation Method of fabricating a stacked via in copper/polyimide beol
US6133139A (en) 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
FR2786609B1 (fr) * 1998-11-26 2003-10-17 St Microelectronics Sa Circuit integre a capacite interlignes reduite et procede de fabrication associe
US6383916B1 (en) * 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US7381642B2 (en) 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6303423B1 (en) 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6869870B2 (en) * 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
SG93278A1 (en) * 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
JP3913927B2 (ja) 1999-04-19 2007-05-09 富士通株式会社 半導体集積回路装置
US6610592B1 (en) 2000-04-24 2003-08-26 Taiwan Semiconductor Manufacturing Company Method for integrating low-K materials in semiconductor fabrication
US6989602B1 (en) * 2000-09-21 2006-01-24 Agere Systems Inc. Dual damascene process with no passing metal features
US6387747B1 (en) * 2001-05-31 2002-05-14 Chartered Semiconductor Manufacturing Ltd. Method to fabricate RF inductors with minimum area
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
US6781217B2 (en) * 2001-12-21 2004-08-24 Intel Corporation Transmission line structure and method of signal propagation
JP3974470B2 (ja) 2002-07-22 2007-09-12 株式会社東芝 半導体装置
KR100871370B1 (ko) * 2002-08-05 2008-12-02 주식회사 하이닉스반도체 반도체소자의 금속배선 형성방법
TWI236763B (en) * 2003-05-27 2005-07-21 Megic Corp High performance system-on-chip inductor using post passivation process
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
CN102157494B (zh) 2005-07-22 2013-05-01 米辑电子股份有限公司 线路组件
US7960797B2 (en) * 2006-08-29 2011-06-14 Micron Technology, Inc. Semiconductor devices including fine pitch arrays with staggered contacts
US8061576B2 (en) 2007-08-31 2011-11-22 Tyco Healthcare Group Lp Surgical instrument
US7624902B2 (en) * 2007-08-31 2009-12-01 Tyco Healthcare Group Lp Surgical stapling apparatus

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US4996133A (en) * 1987-07-31 1991-02-26 Texas Instruments Incorporated Self-aligned tungsten-filled via process and via formed thereby
US5034347A (en) * 1987-10-05 1991-07-23 Menlo Industries Process for producing an integrated circuit device with substrate via hole and metallized backplane
US4832789A (en) * 1988-04-08 1989-05-23 American Telephone And Telegrph Company, At&T Bell Laboratories Semiconductor devices having multi-level metal interconnects
US5010039A (en) * 1989-05-15 1991-04-23 Ku San Mei Method of forming contacts to a semiconductor device
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
FR2663784B1 (fr) * 1990-06-26 1997-01-31 Commissariat Energie Atomique Procede de realisation d'un etage d'un circuit integre.
US5204286A (en) * 1991-10-15 1993-04-20 Micron Technology, Inc. Method of making self-aligned contacts and vertical interconnects to integrated circuits
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5312777A (en) * 1992-09-25 1994-05-17 International Business Machines Corporation Fabrication methods for bidirectional field emission devices and storage structures
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface
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US5300456A (en) * 1993-06-17 1994-04-05 Texas Instruments Incorporated Metal-to-metal antifuse structure
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Also Published As

Publication number Publication date
KR20000067907A (ko) 2000-11-25
DE69709870D1 (de) 2002-02-28
WO1998003994A1 (en) 1998-01-29
US5827776A (en) 1998-10-27
EP0912996A1 (en) 1999-05-06
KR100442407B1 (ko) 2004-07-30
EP0912996B1 (en) 2002-01-02
JP2000515323A (ja) 2000-11-14

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Legal Events

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8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY