DE69621113T2 - Emulationssystem - Google Patents

Emulationssystem

Info

Publication number
DE69621113T2
DE69621113T2 DE69621113T DE69621113T DE69621113T2 DE 69621113 T2 DE69621113 T2 DE 69621113T2 DE 69621113 T DE69621113 T DE 69621113T DE 69621113 T DE69621113 T DE 69621113T DE 69621113 T2 DE69621113 T2 DE 69621113T2
Authority
DE
Germany
Prior art keywords
emulation system
emulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69621113T
Other languages
English (en)
Other versions
DE69621113D1 (de
Inventor
Kiyomi Yamashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69621113D1 publication Critical patent/DE69621113D1/de
Publication of DE69621113T2 publication Critical patent/DE69621113T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69621113T 1995-12-27 1996-12-27 Emulationssystem Expired - Fee Related DE69621113T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7341521A JP2793540B2 (ja) 1995-12-27 1995-12-27 エミュレーション装置

Publications (2)

Publication Number Publication Date
DE69621113D1 DE69621113D1 (de) 2002-06-13
DE69621113T2 true DE69621113T2 (de) 2002-12-19

Family

ID=18346715

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69621113T Expired - Fee Related DE69621113T2 (de) 1995-12-27 1996-12-27 Emulationssystem

Country Status (4)

Country Link
US (1) US5864694A (de)
EP (1) EP0782073B1 (de)
JP (1) JP2793540B2 (de)
DE (1) DE69621113T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
US7024539B2 (en) * 2000-07-17 2006-04-04 Silicon Laboratories Inc. Resistor identification configuration circuitry and associated method
GB0121990D0 (en) * 2001-09-11 2001-10-31 Beach Solutions Ltd Emulation system & method
EP1452968A4 (de) * 2001-11-30 2010-03-03 Fujitsu Ten Ltd Entwicklungsvorrichtung für mikrocomputerlogik
JP4265440B2 (ja) * 2004-02-24 2009-05-20 株式会社デンソー マイクロコンピュータ及びエミュレーション装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
FR2628454B1 (fr) * 1988-03-08 1990-11-16 Cofpa Dispositif de rapprochement sous tension de deux extremites d'une bande large devant revetir une surface en particulier un cylindre de machine a papier
JPH0668189B2 (ja) 1988-06-29 1994-08-31 小松ウォール工業株式会社 吊り天井システム
JPH071500B2 (ja) * 1989-10-20 1995-01-11 日本電気株式会社 シングルチップマイクロコンピュータ
JPH05334460A (ja) 1992-06-03 1993-12-17 Nec Corp シングルチップマイクロコンピュータ
FR2696561B1 (fr) * 1992-10-02 1994-12-23 Sgs Thomson Microelectronics Micro-calculateur pouvant fonctionner en mode d'émulation avec des périphériques internes et externes.
JPH0728665A (ja) * 1993-07-07 1995-01-31 Nec Corp マイクロコンピュータ用エミュレーション装置
US5426769A (en) * 1993-08-26 1995-06-20 Metalink Corp. System and method for producing input/output expansion for single chip microcomputers

Also Published As

Publication number Publication date
US5864694A (en) 1999-01-26
EP0782073A2 (de) 1997-07-02
JP2793540B2 (ja) 1998-09-03
EP0782073A3 (de) 1997-12-29
JPH09179749A (ja) 1997-07-11
DE69621113D1 (de) 2002-06-13
EP0782073B1 (de) 2002-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee