DE69614875T2 - Verfahren und schaltung zur aufrechterhaltung des synchronisierten zustandes in einem digitalen phasenregelkreis - Google Patents

Verfahren und schaltung zur aufrechterhaltung des synchronisierten zustandes in einem digitalen phasenregelkreis

Info

Publication number
DE69614875T2
DE69614875T2 DE69614875T DE69614875T DE69614875T2 DE 69614875 T2 DE69614875 T2 DE 69614875T2 DE 69614875 T DE69614875 T DE 69614875T DE 69614875 T DE69614875 T DE 69614875T DE 69614875 T2 DE69614875 T2 DE 69614875T2
Authority
DE
Germany
Prior art keywords
circuit
signal
pll
maintaining
ckrif
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69614875T
Other languages
English (en)
Other versions
DE69614875D1 (de
Inventor
Maurizio Viti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Information and Communication Networks SpA
Siemens Communications Inc
Original Assignee
Siemens Information and Communication Networks SpA
Siemens Information and Communication Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Information and Communication Networks SpA, Siemens Information and Communication Networks Inc filed Critical Siemens Information and Communication Networks SpA
Publication of DE69614875D1 publication Critical patent/DE69614875D1/de
Application granted granted Critical
Publication of DE69614875T2 publication Critical patent/DE69614875T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H03L7/145—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop the switched reference signal being derived from the controlled oscillator output signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69614875T 1995-12-20 1996-10-10 Verfahren und schaltung zur aufrechterhaltung des synchronisierten zustandes in einem digitalen phasenregelkreis Expired - Fee Related DE69614875T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT95MI002679A IT1278538B1 (it) 1995-12-20 1995-12-20 Procedimento per il mantenimento dell'aggancio in un pll digitale durante eventuali interruzioni transitorie del segnale sincronizzante
PCT/EP1996/004405 WO1997023049A1 (en) 1995-12-20 1996-10-10 Procedure and circuit for holding lock state in a digital pll

Publications (2)

Publication Number Publication Date
DE69614875D1 DE69614875D1 (de) 2001-10-04
DE69614875T2 true DE69614875T2 (de) 2002-04-11

Family

ID=11372753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69614875T Expired - Fee Related DE69614875T2 (de) 1995-12-20 1996-10-10 Verfahren und schaltung zur aufrechterhaltung des synchronisierten zustandes in einem digitalen phasenregelkreis

Country Status (5)

Country Link
EP (1) EP0868783B1 (de)
AT (1) ATE205028T1 (de)
DE (1) DE69614875T2 (de)
IT (1) IT1278538B1 (de)
WO (1) WO1997023049A1 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH566089A5 (de) * 1973-12-20 1975-08-29 Hasler Ag
JPS57140034A (en) * 1981-02-24 1982-08-30 Nec Corp Phase synchronizing oscillator
DE3302700A1 (de) * 1983-01-27 1984-08-02 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum einstellen der mittenfrequenz des oszillators eines phasenregelkreises
EP0479237B1 (de) * 1990-10-02 1997-08-20 Nec Corporation Phasensynchronisiertes Oszillatorsystem mit Ma nahmen gegen Unterbrechung des Eingangstakts

Also Published As

Publication number Publication date
DE69614875D1 (de) 2001-10-04
ITMI952679A1 (it) 1997-06-20
EP0868783A1 (de) 1998-10-07
ITMI952679A0 (de) 1995-12-20
IT1278538B1 (it) 1997-11-24
WO1997023049A1 (en) 1997-06-26
ATE205028T1 (de) 2001-09-15
EP0868783B1 (de) 2001-08-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee