CH566089A5 - - Google Patents

Info

Publication number
CH566089A5
CH566089A5 CH1788973A CH1788973A CH566089A5 CH 566089 A5 CH566089 A5 CH 566089A5 CH 1788973 A CH1788973 A CH 1788973A CH 1788973 A CH1788973 A CH 1788973A CH 566089 A5 CH566089 A5 CH 566089A5
Authority
CH
Switzerland
Application number
CH1788973A
Original Assignee
Hasler Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hasler Ag filed Critical Hasler Ag
Priority to CH1788973A priority Critical patent/CH566089A5/xx
Priority to DE19742456742 priority patent/DE2456742A1/de
Priority to GB5339174A priority patent/GB1452559A/en
Priority to NL7416281A priority patent/NL7416281A/xx
Priority to SE7415990A priority patent/SE398423B/xx
Priority to JP49145849A priority patent/JPS50115458A/ja
Priority to IT70707/74A priority patent/IT1032558B/it
Publication of CH566089A5 publication Critical patent/CH566089A5/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
CH1788973A 1973-12-20 1973-12-20 CH566089A5 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CH1788973A CH566089A5 (de) 1973-12-20 1973-12-20
DE19742456742 DE2456742A1 (de) 1973-12-20 1974-11-30 Verfahren zur erzeugung des n-fachen einer normalfrequenz
GB5339174A GB1452559A (en) 1973-12-20 1974-12-10 Method and device for frequency multiplication
NL7416281A NL7416281A (nl) 1973-12-20 1974-12-13 Werkwijze en inrichting voor het opwekken van het n-voudige van een standaard-frequentie.
SE7415990A SE398423B (sv) 1973-12-20 1974-12-19 Forfarande och anordning for alstring av den n-faldiga faktorn av en normalfrekvens
JP49145849A JPS50115458A (de) 1973-12-20 1974-12-20
IT70707/74A IT1032558B (it) 1973-12-20 1974-12-20 Sistema per generare un multiplon di una frequenza normale

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1788973A CH566089A5 (de) 1973-12-20 1973-12-20

Publications (1)

Publication Number Publication Date
CH566089A5 true CH566089A5 (de) 1975-08-29

Family

ID=4428858

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1788973A CH566089A5 (de) 1973-12-20 1973-12-20

Country Status (7)

Country Link
JP (1) JPS50115458A (de)
CH (1) CH566089A5 (de)
DE (1) DE2456742A1 (de)
GB (1) GB1452559A (de)
IT (1) IT1032558B (de)
NL (1) NL7416281A (de)
SE (1) SE398423B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE7411960L (sv) * 1974-09-24 1976-03-25 Fabriker As Haustrups Sett att framstella behallare sasom flaskor eller burkar av polyester
US4290028A (en) * 1979-07-30 1981-09-15 International Telephone And Telegraph Corporation High speed phase locked loop frequency synthesizer
JPS5720052A (en) 1980-07-11 1982-02-02 Toshiba Corp Input data synchronizing circuit
JPS6051312B2 (ja) * 1981-03-20 1985-11-13 日本ビクター株式会社 水平走査周波数逓倍回路
US4389622A (en) * 1981-09-28 1983-06-21 Honeywell Inc. System for preventing transient induced errors in phase locked loop
JPS58191573A (ja) * 1982-05-06 1983-11-08 Victor Co Of Japan Ltd 水平走査周波数逓倍回路
GB2132042B (en) * 1982-12-15 1986-09-24 British Broadcasting Corp Frequency and timing sources
FR2710806B1 (fr) * 1993-09-28 1995-11-10 France Telecom Dispositif d'asservissement de fréquence.
US5410368A (en) * 1993-12-29 1995-04-25 Zenith Electronics Corp. Carrier acquisition by applying substitute pilot to a synchronous demodulator during a start up interval
IT1278538B1 (it) * 1995-12-20 1997-11-24 Sits Soc It Telecom Siemens Procedimento per il mantenimento dell'aggancio in un pll digitale durante eventuali interruzioni transitorie del segnale sincronizzante
WO1999013582A1 (en) * 1997-09-09 1999-03-18 Advanced Fibre Communications, Inc. Perturbation tolerant digital phase-locked loop employing phase-frequency detector
EP2158677B1 (de) 2007-06-14 2018-05-30 NXP USA, Inc. Schaltungsanordnung zum filtern unerwünschter signale aus einem taktsignal, verarbeitungssystem und verfahren zum filtern unerwünschter signale aus einem taktsignal
WO2010076667A1 (en) 2009-01-05 2010-07-08 Freescale Semiconductor, Inc. Clock glitch detection circuit
WO2010112969A1 (en) 2009-03-31 2010-10-07 Freescale Semiconductor, Inc. Clock glitch detection

Also Published As

Publication number Publication date
SE398423B (sv) 1977-12-19
GB1452559A (en) 1976-10-13
JPS50115458A (de) 1975-09-10
NL7416281A (nl) 1975-06-24
SE7415990L (de) 1975-06-23
IT1032558B (it) 1979-06-20
DE2456742A1 (de) 1975-06-26

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Legal Events

Date Code Title Description
PL Patent ceased