WO2002049248A3 - Demultiplexer for high data rate signals - Google Patents

Demultiplexer for high data rate signals Download PDF

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Publication number
WO2002049248A3
WO2002049248A3 PCT/US2001/048696 US0148696W WO0249248A3 WO 2002049248 A3 WO2002049248 A3 WO 2002049248A3 US 0148696 W US0148696 W US 0148696W WO 0249248 A3 WO0249248 A3 WO 0249248A3
Authority
WO
WIPO (PCT)
Prior art keywords
tdm
demultiplexer
electrical
signals
data
Prior art date
Application number
PCT/US2001/048696
Other languages
French (fr)
Other versions
WO2002049248A2 (en
Inventor
Michael Lagasse
Hemonth Rao
Larry Kushner
Morris Kesler
Original Assignee
Axe Inc
Michael Lagasse
Hemonth Rao
Larry Kushner
Morris Kesler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axe Inc, Michael Lagasse, Hemonth Rao, Larry Kushner, Morris Kesler filed Critical Axe Inc
Priority to EP01988323A priority Critical patent/EP1344340A2/en
Priority to AU2002241640A priority patent/AU2002241640A1/en
Publication of WO2002049248A2 publication Critical patent/WO2002049248A2/en
Publication of WO2002049248A3 publication Critical patent/WO2002049248A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/206—Arrangements for detecting or preventing errors in the information received using signal quality detector for modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/20—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Optical Communication System (AREA)

Abstract

A demultiplexer for Time Division Multiplexed (TDM) signals is described. The demultiplexer includes an electrical splitter that separates an electrical TDM data signal into multiple electrical TDM data signals. A clock recovery circuit generates a clock signal that is synchronized to the electrical TDM data signal and that has a frequency that is harmonically related to a single TDM channel data rate. A phase shifter adjusts the phase of the clock signal. The demultiplexer also includes multiple decision circuits each having a data input for receiving the electrical TDM data signal. Each of the decision circuits also has a clock input that is electrically coupled to an output of the clock recovery circuit for receiving the clock signal. Each of the decision circuits generates demultiplexed TDM signals. The phase shifter is adjusted so that the desired data in each of the demultiplexed TDM signals is selected.
PCT/US2001/048696 2000-12-14 2001-12-12 Demultiplexer for high data rate signals WO2002049248A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01988323A EP1344340A2 (en) 2000-12-14 2001-12-12 Demultiplexer for high data rate signals
AU2002241640A AU2002241640A1 (en) 2000-12-14 2001-12-12 Demultiplexer for high data rate signals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73766800A 2000-12-14 2000-12-14
US09/737,668 2000-12-14

Publications (2)

Publication Number Publication Date
WO2002049248A2 WO2002049248A2 (en) 2002-06-20
WO2002049248A3 true WO2002049248A3 (en) 2003-01-16

Family

ID=24964804

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/048696 WO2002049248A2 (en) 2000-12-14 2001-12-12 Demultiplexer for high data rate signals

Country Status (3)

Country Link
EP (1) EP1344340A2 (en)
AU (1) AU2002241640A1 (en)
WO (1) WO2002049248A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655486B (en) * 2005-03-08 2011-04-20 东南大学 Time division multiplexing one-to-four channel tapping device
EP2319394A1 (en) * 2009-11-05 2011-05-11 Rus Medical Technology S.A. Non-invasive device and method for monitoring analytes in biological samples

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4414364A1 (en) * 1994-04-25 1995-10-26 Siemens Ag Clock pulse recovery by PLL for regeneration of high-speed digital signals
WO1997001901A1 (en) * 1995-06-26 1997-01-16 Siemens Aktiengesellschaft Clock and data regenerator for gigabit signals
US6075825A (en) * 1998-01-06 2000-06-13 Lucent Technologies, Inc. Timing and data recovery circuit for ultra high speed optical communication system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4414364A1 (en) * 1994-04-25 1995-10-26 Siemens Ag Clock pulse recovery by PLL for regeneration of high-speed digital signals
WO1997001901A1 (en) * 1995-06-26 1997-01-16 Siemens Aktiengesellschaft Clock and data regenerator for gigabit signals
US6075825A (en) * 1998-01-06 2000-06-13 Lucent Technologies, Inc. Timing and data recovery circuit for ultra high speed optical communication system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HU T H ET AL: "A MONOLITHIC 480 MB/S PARALLEL AGC/DECISION/COCK-RECOVERY CIRCUIT IN 1.2- M CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 28, no. 12, 1 December 1993 (1993-12-01), pages 1314 - 1320, XP000435905, ISSN: 0018-9200 *
YONEYAMA M ET AL: "FULLY ELECTRICAL 40-GBIT/S TDM SYSTEM PROTOTYPE AND ITS APPLICATIONTO160-GBIT/S WDM TRANSMISSION", OFC/IOOC '99 OPTICAL FIBER COMMUNICATION CONFERENCE / INTERNATIONAL CONFERENCE ON INTEGRATED OPTICS AND OPTICAL FIBER COMMUNICATION. SAN DIEGO, CA, FEB. 21 - 26, 1999, OPTICAL FIBER COMMUNICATION CONFERENCE / INTERNATIONAL CONFERENCE ON INTEGRATED OP, 21 February 1999 (1999-02-21), pages THI6 - 1-THI6-3, XP000967006, ISBN: 0-7803-5430-3 *

Also Published As

Publication number Publication date
AU2002241640A1 (en) 2002-06-24
EP1344340A2 (en) 2003-09-17
WO2002049248A2 (en) 2002-06-20

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