CN1655486B - Time division multiplexing one-to-four channel tapping device - Google Patents
Time division multiplexing one-to-four channel tapping device Download PDFInfo
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- CN1655486B CN1655486B CN 200510038024 CN200510038024A CN1655486B CN 1655486 B CN1655486 B CN 1655486B CN 200510038024 CN200510038024 CN 200510038024 CN 200510038024 A CN200510038024 A CN 200510038024A CN 1655486 B CN1655486 B CN 1655486B
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Abstract
This invention discloses a time complex one to four path connection device to increase system data transmission speed, which comprises one to two frequency divider; first one to two separate connection device and second one to two device. The divider input end is clock input end and the divider two ends are separately connected to the first and second one to two connection device. There is located with displacement device between the first and second dividers. The fixed displacement input end is connected to the first divider input end as data input end and the fixed displacement output end is connected to the input end of divider.
Description
Technical field
The present invention is a kind of device that is used for one road high-speed serial data branch is connected into four tunnel low-speed parallel data, in particular for promoting the time division multiplexing tapping device of message transmission rate.
Technical background
At present, time division multiplex system all is by to one tunnel at a high speed serial signal tap in addition when receiving, and handles thereby the low speed signal that obtains multichannel offers subordinate's circuit, reaches the purpose of elevator system message transmission rate.In international transmission standard-SDH (Synchronous Digital Hierarchy) (SDH), data rate is divided into the grade of STM-1, STM-4, STM-16, STM-64 and STM-256.Link between each message transmission rate grade is to finish by the multiple connection and the tapping device of four circuit-switched data and a circuit-switched data.The speed of transfer of data grade OC-3, OC-12, OC-48, OC-192 and the OC-768 of the definition of the Synchronous Optical Network standard (SONET) of the U.S. is consistent with STM-1, STM-4, STM-16, STM-64 and STM-256 respectively, and also is by multiple connection and the tapping device lifting that realize transmission rate of four circuit-switched data to one tunnel.Particularly in the transmission rate of STM-256 and OC-768 system-level data up to 40Gbit/s, and adopt forward error correction technique to be increased to 43Gbit/s especially.On this speed grade, one road to four tunnel the multiple connection and the design of tapping device are because data rate becomes difficult unusually near the cut-off frequency of circuit active transistor.The above tapping device of now existing 10Gbit/s generally all is to adopt tree, but this circuit structure common characteristic is: thus the more power consumption in circuit devcie unit that needs is bigger; And, thereby reduced the phase margin of coupler because 1: 4 coupler needs 1: 2 coupler level of two-stage to connect.This has increased the complexity that system realizes, is unfavorable for the product realization simultaneously.
Summary of the invention
The invention provides a kind of time division multiplexing one-to-four channel tapping device that is used to promote message transmission rate and can reduces power consumption, increase phase margin, it can realize the tap of 1 circuit-switched data to 4 circuit-switched data, it is simple to have circuit structure, and the edge between the output signal loses tiltedly little advantage.
The present invention adopts following technical scheme:
A kind of time division multiplexing one-to-four channel tapping device that is used for the elevator system message transmission rate, by 1: 2 frequency divider, the one 1: 2 couplers and the 21: 2 couplers are formed, the input of 1: 2 frequency divider is an input end of clock, two outputs of frequency divider are connected with the input end of clock of the one 1: 2 couplers and the 21: 2 couplers respectively, between the one 1: 2 couplers and the 21: 2 couplers, be provided with fixed phase shifter, the input and the 1 of fixed phase shifter: the input of 2 couplers links to each other and as data input pin, the output and the 21 of fixed phase shifter: the input of 2 couplers is connected.
Compared with prior art, the present invention has following advantage:
The present invention includes: the sequential between 1: 2 tap unit of 1: the 2 tap unit in 1: 2 tap unit of 1: 2 frequency divider, 1/2 clock, two 1/4 clocks and 2 two-stages is adjusted buffer amplifier circuit.Compare with the tree type coupler of realizing said function, 1. the present invention circuit devcie unit of needing has used the sequential between 1: 2 tap unit of 1: 2 tap unit of one 1/2 clock and 2 two-stages to adjust buffer amplifier circuit less; Only increased a transmission line that does not consume any power consumption as fixing phase-shifting unit.On circuit structure, just saved power consumption like this.2. the present invention only utilizes 1/4 clock to carry out tap, thereby has realized the single-stage tap.It is oblique that the complexity that has reduced design so also helps simultaneously the mistake that increases the phase margin of coupler and reduce the edge between four tunnel output signals.3. the present invention is owing to be the operating rate that the single-stage tap can greatly improve coupler.
Description of drawings
Fig. 1 is a block diagram of the present invention.
Fig. 2 is the circuit diagram of embodiment of the present invention.
Fig. 3 is the concrete sequential schematic diagram of circuit of the present invention.
Embodiment
The present invention is a kind of time division multiplexing one-to-four channel tapping device that is used for the elevator system message transmission rate, by 1: 2 frequency divider 1, the one 1: 2 couplers the 2 and the 21: 2 couplers 3 are formed, the input of 1: 2 frequency divider 1 is an input end of clock, two outputs of frequency divider 1 respectively with the one 1: 2 couplers the 2 and the 21: the input end of clock of 2 couplers 3 is connected, between the one 1: 2 couplers the 2 and the 21: 2 couplers 3, be provided with fixed phase shifter 4, the input and the 1 of fixed phase shifter 4: the input of 2 couplers 2 links to each other and as data input pin, the output and the 21 of fixed phase shifter 4: the input of 2 couplers 3 is connected, in ability strength, frequency divider 1 was by rising edge trigger register 11 in 1: 2, trailing edge trigger register 12 and inverter 13 are formed.The input end of clock of rising edge trigger register 11 and trailing edge trigger register 12 is connected and as the input of frequency divider 1, the input and output of inverter 13 link to each other with the output of rising edge trigger register 11 and the input of trailing edge trigger register 12 respectively, 12 outputs link to each other with the trailing edge trigger register in the input of rising edge trigger register 11, and as the output of frequency divider, in the present embodiment, the one 1:2 coupler 2 is by rising edge trigger register 22,24 and trailing edge trigger register 21,23,25 form, rising edge trigger register 22,24 and trailing edge trigger register 21,23,25 input end of clock connects the input end of clock as 1:2 coupler 2, the input of rising edge trigger register 24 and trailing edge trigger register 21 links to each other as the data input pin of 1:2 coupler 2, trailing edge trigger register 21, the output that rising edge trigger register 22 and trailing edge trigger register 23 constitutes serial structures and trailing edge trigger register 23 is illustrated the 2nd output as one tunnel output of 1:2 coupler 2, and the output that rising edge trigger register 24 and trailing edge trigger register 25 constitute serial structures and trailing edge trigger register 25 is illustrated the 4th output as other one tunnel output of 1:2 coupler 2; Above-mentioned the 2nd 1:2 tap unit 3 except data input pin with fixedly the output of phase-shifting unit 4 is connected, line is the same substantially with the line of 1:2 tap unit 2, that is: the 2nd 1:2 tap unit 3 is by rising edge trigger register 32,34 and trailing edge trigger register 31,33,35 form, rising edge trigger register 32,34 and trailing edge trigger register 31,33,35 input end of clock connects the input end of clock as 1:2 coupler 3, the input of rising edge trigger register 34 and trailing edge trigger register 31 links to each other and to be connected with the fixing output of phase-shifting unit 4 as the data input pin of 1:2 coupler 3, trailing edge trigger register 31, rising edge trigger register 32 and trailing edge trigger register 33 constitute road output i.e. 1st output of the output of serial structure and trailing edge trigger register 33 as 1:2 coupler 3, and rising edge trigger register 34 and trailing edge trigger register 35 formation serial structures and 35 outputs of trailing edge trigger register are as i.e. the 3rd output of other one tunnel output of 1:2 coupler 3.Described fixed phase shifter 4 is transmission line structure or cascade amplifier.
The work schedule of circuit of the present invention as shown in Figure 3, the data-signal of input is behind fixed phase shifter, data bit of data at the two ends of fixed phase shifter, therefore see constantly at any one, the two ends of fixed phase shifter all are two adjacent data, so just two adjacent data have been separated.And the frequency of input clock is 1/2 of an input data bit-rate, then is 1/4 of data bit-rate through two divided-frequency, therefore alternately samples under the control of 1/4 clock high-low level at the 1:2 coupler and imports data.And it is owing to be 1/4 clock,, then opposite at the other end in can only the sample data of odd number or even bit of an end of fixed phase shifter.Like this at the two ends of fixed phase shifter in a clock cycle, 4 continuous data taps are become 4 parallel data, the road serial data branch that just will import of clock cycle sex work has been connected into four road data that walk abreast like this.The present invention can be realized by the existing integrated circuits manufacturing process.
Claims (4)
1. time division multiplexing one-to-four channel tapping device that is used for the elevator system message transmission rate, comprise 1: 2 frequency divider (1), the one 1: 2 couplers (2), the 21: 2 couplers (3) and fixed phase shifter (4), 1: 2 frequency divider (1) output and the 1: the input end of clock of 2 couplers (2) and the 21: 2 couplers (3) is connected, the input and the 1 that it is characterized in that fixed phase shifter (4): the data input pin of 2 couplers (2) links to each other, the output and the 21 of fixed phase shifter (4): the input of 2 couplers (3) is connected, data at the two ends of fixed phase shifter differ a data bit, see constantly that at any one the two ends of fixed phase shifter all are two adjacent data.
2. time division multiplexing one-to-four channel tapping device according to claim 1, it is characterized in that 1: 2 frequency divider (1) by rising edge trigger register (11), trailing edge trigger register (12) and inverter (13) are formed, the input end of clock of rising edge trigger register (11) and trailing edge trigger register (12) be connected and as 1: 2 frequency divider (1) input, the input and output of inverter (13) link to each other with the output of rising edge trigger register (11) and the input of trailing edge trigger register (12) respectively, the output of the input of rising edge trigger register (11) and trailing edge trigger register (12) links to each other, and as the output of 1: 2 frequency divider.
3. time division multiplexing one-to-four channel tapping device according to claim 1 is characterized in that fixed phase shifter (4) is microstrip line or coplanar waveguide structure.
4. time division multiplexing one-to-four channel tapping device according to claim 1 is characterized in that fixed phase shifter (4) is an adjustable delay time cascade buffer amplifier.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510038024 CN1655486B (en) | 2005-03-08 | 2005-03-08 | Time division multiplexing one-to-four channel tapping device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510038024 CN1655486B (en) | 2005-03-08 | 2005-03-08 | Time division multiplexing one-to-four channel tapping device |
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| CN1655486A CN1655486A (en) | 2005-08-17 |
| CN1655486B true CN1655486B (en) | 2011-04-20 |
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| CN 200510038024 Expired - Fee Related CN1655486B (en) | 2005-03-08 | 2005-03-08 | Time division multiplexing one-to-four channel tapping device |
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| CN102307085B (en) * | 2011-06-09 | 2014-06-25 | 中国工程物理研究院电子工程研究所 | All-digital single-channel broadband signal generation method and device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5128940A (en) * | 1989-09-11 | 1992-07-07 | Kabushiki Kaisha Toshiba | Demultiplexer |
| CN2151588Y (en) * | 1993-03-24 | 1993-12-29 | 机械电子工业部石家庄第五十四研究所 | General complex connecting unit |
| CN1348269A (en) * | 2001-10-31 | 2002-05-08 | 东南大学 | Physical medium additive sublayer data transmission method and device of gigacycle Ethernet |
| WO2002049248A2 (en) * | 2000-12-14 | 2002-06-20 | Axe, Inc. | Demultiplexer for high data rate signals |
| EP1351419A1 (en) * | 2002-04-03 | 2003-10-08 | Lucent Technologies Inc. | Method and apparatus for barrel shifting of parallel output data signals |
| CN2765403Y (en) * | 2005-03-08 | 2006-03-15 | 东南大学 | Time division one-to-four path tapping device |
-
2005
- 2005-03-08 CN CN 200510038024 patent/CN1655486B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5128940A (en) * | 1989-09-11 | 1992-07-07 | Kabushiki Kaisha Toshiba | Demultiplexer |
| CN2151588Y (en) * | 1993-03-24 | 1993-12-29 | 机械电子工业部石家庄第五十四研究所 | General complex connecting unit |
| WO2002049248A2 (en) * | 2000-12-14 | 2002-06-20 | Axe, Inc. | Demultiplexer for high data rate signals |
| CN1348269A (en) * | 2001-10-31 | 2002-05-08 | 东南大学 | Physical medium additive sublayer data transmission method and device of gigacycle Ethernet |
| EP1351419A1 (en) * | 2002-04-03 | 2003-10-08 | Lucent Technologies Inc. | Method and apparatus for barrel shifting of parallel output data signals |
| CN2765403Y (en) * | 2005-03-08 | 2006-03-15 | 东南大学 | Time division one-to-four path tapping device |
Non-Patent Citations (4)
| Title |
|---|
| 朱恩, 王志功, 等.2.5～40Gb/s光收发关键器件芯片技术.中国有色金属学报第14卷 专辑1.2004,第14卷(专辑1),369-380. |
| 朱恩, 王志功,等.2.5～40Gb/s光收发关键器件芯片技术.中国有色金属学报第14卷 专辑1.2004,第14卷(专辑1),369-380. * |
| 王志功.光纤通信集成电路设计 第1版.高等教育出版社,2003,263-272. |
| 王志功.光纤通信集成电路设计 第1版.高等教育出版社,2003,263-272. * |
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