WO2001047160A3 - Schaltungsanordnung und verfahren zur taktsignalbereitstellung - Google Patents

Schaltungsanordnung und verfahren zur taktsignalbereitstellung Download PDF

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Publication number
WO2001047160A3
WO2001047160A3 PCT/DE2000/003938 DE0003938W WO0147160A3 WO 2001047160 A3 WO2001047160 A3 WO 2001047160A3 DE 0003938 W DE0003938 W DE 0003938W WO 0147160 A3 WO0147160 A3 WO 0147160A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit arrangement
clock signal
signal generation
processes
requirements
Prior art date
Application number
PCT/DE2000/003938
Other languages
English (en)
French (fr)
Other versions
WO2001047160A2 (de
Inventor
Imre Hipp
Original Assignee
Siemens Ag
Imre Hipp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Imre Hipp filed Critical Siemens Ag
Priority to DE10084066T priority Critical patent/DE10084066D2/de
Publication of WO2001047160A2 publication Critical patent/WO2001047160A2/de
Publication of WO2001047160A3 publication Critical patent/WO2001047160A3/de

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Information Transfer Systems (AREA)

Abstract

Mit dieser Schaltungsanordnung und dem dazugehörigen Verfahren kann auf Anforderungen an Prozesse der digitalen Frequenznachsteuerung sowie an Prozesse der Schnittstellenfunktionen durch progammierbare Hardwarefunktionalität flexibel eingegangen werden.
PCT/DE2000/003938 1999-12-22 2000-11-10 Schaltungsanordnung und verfahren zur taktsignalbereitstellung WO2001047160A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10084066T DE10084066D2 (de) 1999-12-22 2000-11-10 Schaltungsanordnung und Verfahren zur Taktsignalbereitstellung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19962217 1999-12-22
DE19962217.5 1999-12-22

Publications (2)

Publication Number Publication Date
WO2001047160A2 WO2001047160A2 (de) 2001-06-28
WO2001047160A3 true WO2001047160A3 (de) 2002-02-07

Family

ID=7933939

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/003938 WO2001047160A2 (de) 1999-12-22 2000-11-10 Schaltungsanordnung und verfahren zur taktsignalbereitstellung

Country Status (3)

Country Link
CN (1) CN1435021A (de)
DE (1) DE10084066D2 (de)
WO (1) WO2001047160A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10329116B3 (de) * 2003-06-27 2004-12-09 Siemens Ag Verfahren und Vorrichtung zur Zeitbildung in einer Datenverarbeitungseinheit
CN112769518B (zh) * 2021-01-22 2022-09-13 上海宽域工业网络设备有限公司 一种带秒准时沿的串口时间发送系统及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
EP0631407A2 (de) * 1993-06-07 1994-12-28 Alcatel STR AG Verfahren und Vorrichtung zum phasengenauen Umschalten gleichgearteter Impulszüge mit unterschiedlicher Phasenlage
US5666330A (en) * 1994-07-21 1997-09-09 Telecom Solutions, Inc. Disciplined time scale generator for primary reference clocks
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
WO1999011017A1 (en) * 1997-08-28 1999-03-04 Ascend Communications, Inc. Timing synchronization and switchover in a network switch
CA2217840A1 (en) * 1997-10-09 1999-04-09 Northern Telecom Limited Synchronization system multiple modes of operation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
EP0631407A2 (de) * 1993-06-07 1994-12-28 Alcatel STR AG Verfahren und Vorrichtung zum phasengenauen Umschalten gleichgearteter Impulszüge mit unterschiedlicher Phasenlage
US5666330A (en) * 1994-07-21 1997-09-09 Telecom Solutions, Inc. Disciplined time scale generator for primary reference clocks
WO1999011017A1 (en) * 1997-08-28 1999-03-04 Ascend Communications, Inc. Timing synchronization and switchover in a network switch
CA2217840A1 (en) * 1997-10-09 1999-04-09 Northern Telecom Limited Synchronization system multiple modes of operation

Also Published As

Publication number Publication date
WO2001047160A2 (de) 2001-06-28
CN1435021A (zh) 2003-08-06
DE10084066D2 (de) 2003-01-30

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