AU2001290945A1 - Digital system of adjusting delays on circuit boards - Google Patents

Digital system of adjusting delays on circuit boards

Info

Publication number
AU2001290945A1
AU2001290945A1 AU2001290945A AU9094501A AU2001290945A1 AU 2001290945 A1 AU2001290945 A1 AU 2001290945A1 AU 2001290945 A AU2001290945 A AU 2001290945A AU 9094501 A AU9094501 A AU 9094501A AU 2001290945 A1 AU2001290945 A1 AU 2001290945A1
Authority
AU
Australia
Prior art keywords
circuit boards
digital system
adjusting delays
delays
adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001290945A
Inventor
Randy M Bonella
John Halbert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001290945A1 publication Critical patent/AU2001290945A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
AU2001290945A 2000-09-15 2001-09-14 Digital system of adjusting delays on circuit boards Abandoned AU2001290945A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/662,054 US6928571B1 (en) 2000-09-15 2000-09-15 Digital system of adjusting delays on circuit boards
US09/662,054 2000-09-15
PCT/US2001/028805 WO2002023358A2 (en) 2000-09-15 2001-09-14 Digital system of adjusting delays on circuit boards

Publications (1)

Publication Number Publication Date
AU2001290945A1 true AU2001290945A1 (en) 2002-03-26

Family

ID=24656192

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001290945A Abandoned AU2001290945A1 (en) 2000-09-15 2001-09-14 Digital system of adjusting delays on circuit boards

Country Status (6)

Country Link
US (1) US6928571B1 (en)
KR (1) KR100740076B1 (en)
CN (1) CN1295628C (en)
AU (1) AU2001290945A1 (en)
TW (1) TWI242721B (en)
WO (1) WO2002023358A2 (en)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067594A (en) * 1997-09-26 2000-05-23 Rambus, Inc. High frequency bus system
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
US6646953B1 (en) 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
DE60237301D1 (en) 2001-10-22 2010-09-23 Rambus Inc PHASE ADJUSTMENT DEVICE AND METHOD FOR A MEMORY MODULE SIGNALING SYSTEM
US7170907B1 (en) * 2002-02-15 2007-01-30 Marvell Semiconductor Israel Ltd. Dynamic alignment for data on a parallel bus
DE102004016337A1 (en) * 2004-04-02 2005-10-27 Siemens Ag Receiver circuit for receiving signals from multiple transmitters and or senders has a receiving register with a programmable delay element that is controlled so that incoming signals match the register time rules
US7669027B2 (en) * 2004-08-19 2010-02-23 Micron Technology, Inc. Memory command delay balancing in a daisy-chained memory topology
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
KR101271245B1 (en) 2005-04-21 2013-06-07 바이올린 메모리 인코포레이티드 Interconnection System
US9286198B2 (en) 2005-04-21 2016-03-15 Violin Memory Method and system for storage of data in non-volatile media
US9582449B2 (en) 2005-04-21 2017-02-28 Violin Memory, Inc. Interconnection system
US8452929B2 (en) 2005-04-21 2013-05-28 Violin Memory Inc. Method and system for storage of data in non-volatile media
US8112655B2 (en) 2005-04-21 2012-02-07 Violin Memory, Inc. Mesosynchronous data bus apparatus and method of data transmission
US9384818B2 (en) 2005-04-21 2016-07-05 Violin Memory Memory power management
US8028186B2 (en) 2006-10-23 2011-09-27 Violin Memory, Inc. Skew management in an interconnection system
JP4821907B2 (en) 2007-03-06 2011-11-24 日本電気株式会社 Memory access control system, memory access control method and program thereof
US20100185810A1 (en) * 2007-06-12 2010-07-22 Rambus Inc. In-dram cycle-based levelization
US8689218B1 (en) 2008-10-15 2014-04-01 Octasic Inc. Method for sharing a resource and circuit making use of same
US8543750B1 (en) 2008-10-15 2013-09-24 Octasic Inc. Method for sharing a resource and circuit making use of same
CN104593742B (en) * 2015-01-20 2017-02-22 清华大学深圳研究生院 Equipment and method for preparing oxide film with biaxial texture
DE102017109456A1 (en) * 2017-05-03 2018-11-08 Carl Zeiss Microscopy Gmbh Microscope system and method for operating a microscope system
CN115129642B (en) * 2022-06-14 2023-09-08 沐曦集成电路(南京)有限公司 Chip bus delay adjustment method, electronic equipment and medium
CN115129641B (en) * 2022-06-14 2024-01-19 沐曦集成电路(南京)有限公司 Bidirectional interconnection bus delay adjustment method, electronic equipment and medium

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE273732C (en)
DD273732A1 (en) * 1988-07-01 1989-11-22 Univ Dresden Tech DEVICE FOR AUTOMATICALLY COMPARING DURATION DIFFERENCES OF SEVERAL TRANSMISSION CHANNELS
US5267240A (en) 1992-02-20 1993-11-30 International Business Machines Corporation Frame-group transmission and reception for parallel/serial buses
US5615358A (en) 1992-05-28 1997-03-25 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor
JP2889113B2 (en) 1994-04-26 1999-05-10 インターナショナル・ビジネス・マシーンズ・コーポレイション Delay generation device, data processing system and data transmission system
JPH08123717A (en) 1994-10-25 1996-05-17 Oki Electric Ind Co Ltd Semiconductor storage device
JP3233801B2 (en) * 1994-12-09 2001-12-04 沖電気工業株式会社 Bit phase synchronization circuit
US6292903B1 (en) * 1997-07-09 2001-09-18 International Business Machines Corporation Smart memory interface
US6105144A (en) 1998-03-02 2000-08-15 International Business Machines Corporation System and method for alleviating skew in a bus
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6041419A (en) * 1998-05-27 2000-03-21 S3 Incorporated Programmable delay timing calibrator for high speed data interface
US6430696B1 (en) * 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6654897B1 (en) 1999-03-05 2003-11-25 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US6629222B1 (en) * 1999-07-13 2003-09-30 Micron Technology Inc. Apparatus for synchronizing strobe and data signals received from a RAM

Also Published As

Publication number Publication date
CN1484793A (en) 2004-03-24
TWI242721B (en) 2005-11-01
CN1295628C (en) 2007-01-17
WO2002023358A2 (en) 2002-03-21
KR100740076B1 (en) 2007-07-18
KR20030048042A (en) 2003-06-18
WO2002023358A3 (en) 2003-03-06
US6928571B1 (en) 2005-08-09

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