DE102004016337A1 - Receiver circuit for receiving signals from multiple transmitters and or senders has a receiving register with a programmable delay element that is controlled so that incoming signals match the register time rules - Google Patents

Abstract

Receiver circuit (100) for an integrated circuit has the following: a receiving register (102) for accepting input signals into the integrated circuit; a delay element (104) prior to the register to match the input signals to the time rules in the receiving register and; a control unit (106) for determining which of a multiplicity of possible transmitters is delivering an input signal and for matching the programmable delay element to the time properties of the signal transmitted by the transmitter. The invention also relates to a circuit arrangement with a multiplicity of transmitters and a receiver with an inventive receiver circuit.

Description

The The present invention relates to a receiving circuit or input circuit, especially for integrated circuits.

Lots Electronic circuits have structures in which receiver modules via Sianlleitungen receive signals from transmitters.

There electronic circuits and in particular circuits for signal processing usually are clocked Arrangements are made to ensure that one over one the signal lines transmitted Signal is applied to a register of a receiver module exactly then, when this register is ready to receive the signal. These Willingness to take up will be provided by a register attached to the register Clock signal controlled. In other words, it must be ensured that the setup and hold times of the register are complied with. This is usually by a delay element, which precedes the register input reached.

For receiver modules, that of several transmitters arranged at different distances Receive signals must - for each transmitter separately - receive circuits or input circuits are provided, the delay elements the different ones resulting from the different distances Compensate signal propagation times. The disadvantage here is that many receiving circuits provided in a receiver module Need to become.

Of the The invention has for its object to provide a receiving circuit, which can receive the signals of several transmitters by the number reduce the receiving circuits in a receiver module.

• – ein Übernahmeregister zur Übernahme von Eingangssignalen in den integrierten Schaltkreis;
• – ein dem Übernahmeregister vorgeschaltetes programmierbares Verzögerungsglied zur Anpassung der Eingangssignale an Zeitvorgaben des Übernahmeregisters; und
• – eine Steuerung zum Ermitteln, welcher einer Mehrzahl möglicher Sender Eingangssignale liefert, und zum Anpassen des programmierbaren Verzögerungsgliedes an die Zeiteigenschaften der von dem ermittelten Sender gelieferten Eingangssignale.

This object is achieved by a receiving circuit of an integrated circuit, which has the following:

• A takeover register for accepting input signals to the integrated circuit;
• A programmable delay element connected upstream of the transfer register for adapting the input signals to time specifications of the transfer register; and
• A controller for determining which of a plurality of possible transmitters supplies input signals and for adapting the programmable delay element to the time characteristics of the input signals supplied by the detected transmitter.

The Reception circuit may additionally a memory for storing a delay value for each the possible Transmitters have. When signals are received from a particular transmitter, the delay value assigned to this transmitter is correspondingly off retrieved from the memory and passed to the delay element.

The Reception circuit may additionally a data edge detection for determining the time characteristics of from the programmable delay element delayed Have input signals. In a learning mode can by appropriate Programming the delay element be achieved that this causes no delay, so that in learning mode the different signal delays between the different ones Transmitters and the receiving circuit, by the different lengths Signal lines are caused, can be determined.

By the controller may have an optimal delay value for the programmable delay be determined based on the signal transit times so that the sum from signal delay and delay to a valid Signal at the input of the transfer register leads (i.e. a signal that meets the setup and hold times requirements of the Register fulfilled). The determined delay values are then stored in memory.

It is possible, the determination of the optimal deceleration value in normal operation e.g. repeat periodically to detect changes in signal transit times, e.g. caused by temperature fluctuations, to take into account.

Of the Exchange of control information and status information between Control, delay element, Memory and data edge detection can be done via a control bus. additionally can be provided that the controller an arbitration signal receives to determine the transmitting station.

The inventive receiving circuit can preferably in a receiver be used in a circuit arrangement, which a plurality of transmitters and having only one receiver, the transmitters having one common data bus coupled to the receiving circuit. Further For example, the circuitry may arbitrate an arbitration bus among the transmitters, wherein the receiving circuit also connected to the Arbitrierungsbus.

For the circuit arrangement can be a learning mode, which is activated during the initialization of the circuit arrangement, wherein in the learning mode, all transmitters successively supply signals to the receiver, in the receiving circuit, as explained above, the time characteristics of the signals are determined and determined from the time characteristics delay values for the programmable delay element and be stored in memory.

One Advantage of the invention is the fact that for any number of Senders a receive circuit is sufficient to timely, i.e. respecting the setup and Hold times, in an input buffer of a receiver abzufakten. Especially This advantage becomes clear with a large number of transmitters so far an equally large Number of receiving circuits required, their area requirements on an integrated circuit was correspondingly large.

in the The following will be an embodiment of Present invention explained in more detail with reference to two figures. Show:

1 a preferred form of the receiving circuit according to the invention in a schematic representation, and

2 a circuit arrangement in a schematic representation, comprising a plurality of transmitters and a receiver comprising a receiving circuit according to the invention.

In 1 is an embodiment of the receiving circuit according to the invention 100 shown schematically. For example, from a data bus (not in 1 shown) input data via a programmable delay element 104 to a takeover register 102 which then feeds the input data isochronously to a subsequent signal processing circuit (not in 1 shown).

Also in the takeover register 102 is input a clock, which corresponds for example to the system clock, and preferably with the clock of transmitting devices 210 (please refer 2 ) is synchronous.

The through the programmable delay element 104 The delay applied to the input signal is predetermined such that the signal present at the input of the transfer register does not violate the setup and hold times of the register.

This is done in a memory 108 for any transmitter 210A - 210N reserved separately a delay value. Through a controller 106 it is determined from which of the possible transmitters 210 each at the delay element 104 received signals, and the corresponding delay value is retrieved from the memory and used to program the delay element. For this, the controller 106 evaluate any signal that the transmitters 210 to grant a send authorization. A suitable signal is, for example, a so-called Arbitrierungssignal, which by the controller 106 can be evaluated and indicates which station is allowed to send or send at a certain time. The type of arbitration is unimportant, as long as a specific arbitration state can be unambiguously assigned to a specific sender.

The in the store 108 stored delay values can either be determined during the development process and predefined, or determined during system initialization in a learning mode. For this purpose, a data edge detection 110 can be used, as it is known for example from the publication WO 98/49802. Other methods for determining the time characteristics of the input signals may also be used.

In an exemplary learning mode, by appropriately programming the delay element 104 be achieved that this causes no delay, so that in the learning mode, the different signal propagation times between the different transmitters 210 and the receiving circuit 100 which are caused by the signal lines of different lengths, by the data edge detection 110 can be determined.

Subsequently, all transmitters are caused to send a signal in a predetermined order. Thus, it is initially possible, the signal propagation times for each of the transmitter 210 to investigate.

Through the controller 106 can be an optimal delay value for the programmable delay element 104 be determined based on the signal propagation times so that the sum of signal delay and delay to a valid signal at the input of the transfer register 102 results (ie a signal that meets the setup and hold times requirements of the register). The one for each of the transmitters 210A -N-determined delay value is then stored in memory 108 stored.

It is possible to periodically repeat the determination of the optimum delay value in normal operation, for example, in order to take into account changes in the signal propagation times, eg caused by temperature fluctuations. It goes without saying that the adaptation of the delays values only occurs if a deviation of the values for the signal propagation times is determined for a specific transmitter compared to the last determination.

An exemplary circuit arrangement 200 in which the receiving circuit according to the invention 100 can be used advantageously is in 2 shown. 2 shows next to the n transmitters 210A - 210N a common data bus 206 over which the transmitters 210A - 210N Data to a common receiver 202 can send. This receiver points next to the receiving circuit 100 a signal processing circuit 204 on.

To control access to the shared data bus 206 serves an Arbitrierungsbus, for example, according to the "round robin" principle send permissions to the transmitter 210 granted. This arbitration bus 208 and its control also support the learning mode described above in the initialization phase of the circuit 200 ,

It it can be provided that the transmitters transmit test data, if no user data for transmission pending the monitoring the signal delay and the possibly subsequent redetermination of the optimal delay value carry out to be able to.

Claims (8)

Receiving circuit ( 100 ) of an integrated circuit comprising: - a takeover register ( 102 ) for accepting input signals to the integrated circuit; A programmable delay element upstream of the transfer register ( 104 ) for adapting the input signals to timings of the transfer register ( 102 ); and a controller ( 106 ) for determining which of a plurality of possible transmitters ( 210 ) Provides input signals, and for adapting the programmable delay element ( 104 ) to the time characteristics of the input signals provided by the detected transmitter. Receiving circuit ( 100 ) according to claim 1, additionally comprising a memory ( 108 ) for storing a delay value for each of the possible transmitters ( 210 ), wherein the controller ( 106 ) additionally means for retrieving the delay value for the determined transmitter from the memory ( 108 ) and means for transmitting the delay value to the delay element ( 104 ) having. Receiving circuit ( 100 ) according to claim 2, additionally comprising data edge detection ( 110 ) for determining the time characteristics of the programmable delay element ( 104 ) has delayed input signals, wherein the controller ( 106 ) additionally means for evaluating the determined time characteristics and means for determining an optimal delay value for the respective transmitter from the determined time characteristics and means for storing the determined optimal delay value in the memory ( 108 ) having. Receiving circuit ( 100 ) according to claim 3, additionally comprising a control bus ( 112 ) for bidirectionally transmitting control information and status information between controllers ( 106 ), Delay element ( 104 ), Storage ( 108 ) and data edge detection ( 110 ) having. Receiving circuit ( 100 ) according to one of Claims 1 to 4, the control of which comprises means for evaluating an arbitration signal for determining which of a plurality of possible transmitters ( 210 ) Provides input signals. Circuit arrangement ( 200 ) comprising a plurality of transmitters ( 210 ) and a receiver ( 202 ) with a receiving circuit ( 100 ) according to one of claims 1 to 5 and a signal processing circuit ( 204 ), where the majority of stations ( 210 ) via a common data bus ( 206 ) with the receiving circuit ( 202 ) is coupled. Circuit arrangement ( 200 ) according to claim 6, additionally comprising an arbitration bus ( 208 ) for arbitration among the stations ( 210 ), wherein the receiving circuit ( 100 ) is connected to the arbitration bus. Circuit arrangement ( 200 ) according to one of claims 6 or 7, additionally comprising means for providing a learning mode in the initialization of the circuit arrangement, wherein in the learning mode all the transmitters ( 210 ) successively signals to the receiver ( 202 ) in whose receiving circuit ( 100 ) the time characteristics of the signals are determined and from the time characteristics delay values for a programmable delay element ( 104 ) of the receiving circuit and in a memory ( 108 ) of the receiving circuit are stored.