DE69612293D1 - Bitverschachtelter 16/17-modulationscode mit dreiwege-byteverschachteltem fehlerkorrekturcode - Google Patents

Bitverschachtelter 16/17-modulationscode mit dreiwege-byteverschachteltem fehlerkorrekturcode

Info

Publication number
DE69612293D1
DE69612293D1 DE69612293T DE69612293T DE69612293D1 DE 69612293 D1 DE69612293 D1 DE 69612293D1 DE 69612293 T DE69612293 T DE 69612293T DE 69612293 T DE69612293 T DE 69612293T DE 69612293 D1 DE69612293 D1 DE 69612293D1
Authority
DE
Germany
Prior art keywords
interleaved
code
bit
error correction
correction code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69612293T
Other languages
English (en)
Other versions
DE69612293T2 (de
Inventor
D Fisher
A Ziperovich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quantum Corp
Original Assignee
Quantum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quantum Corp filed Critical Quantum Corp
Publication of DE69612293D1 publication Critical patent/DE69612293D1/de
Application granted granted Critical
Publication of DE69612293T2 publication Critical patent/DE69612293T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1866—Error detection or correction; Testing, e.g. of drop-outs by interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1434—8 to 9 modulation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1446—16 to 17 modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
DE69612293T 1995-08-24 1996-08-08 Bitverschachtelter 16/17-modulationscode mit dreiwege-byteverschachteltem fehlerkorrekturcode Expired - Fee Related DE69612293T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/518,945 US5757822A (en) 1995-08-24 1995-08-24 Bit-interleaved rate 16/17 modulation code with three-way byte-interleaved ECC
PCT/US1996/012970 WO1997008836A1 (en) 1995-08-24 1996-08-08 Bit-interleaved rate 16/17 modulation code with three-way byte-interleaved ecc

Publications (2)

Publication Number Publication Date
DE69612293D1 true DE69612293D1 (de) 2001-05-03
DE69612293T2 DE69612293T2 (de) 2001-10-18

Family

ID=24066147

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69612293T Expired - Fee Related DE69612293T2 (de) 1995-08-24 1996-08-08 Bitverschachtelter 16/17-modulationscode mit dreiwege-byteverschachteltem fehlerkorrekturcode

Country Status (9)

Country Link
US (1) US5757822A (de)
EP (1) EP0846374B1 (de)
JP (1) JPH11511610A (de)
KR (1) KR19990044116A (de)
CN (1) CN1202992A (de)
AU (1) AU7321498A (de)
CA (1) CA2230132A1 (de)
DE (1) DE69612293T2 (de)
WO (1) WO1997008836A1 (de)

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US5717395A (en) * 1996-07-29 1998-02-10 Cirrus Logic, Inc. Rate 16/17 ENDEC with independent high/low byte decoding
KR100408532B1 (ko) * 1996-10-31 2004-01-24 삼성전자주식회사 데이타저장기기의prml코드생성방법
US5784010A (en) * 1997-02-03 1998-07-21 International Business Machines Corporation Method and apparatus for implementing a set rate code for data channels with alternate 9-bit code words and 8-bit code words
US6035435A (en) * 1997-09-30 2000-03-07 Datapath Systems, Inc. Method and apparatus for encoding a binary signal
EP0913762A1 (de) * 1997-10-31 1999-05-06 Hewlett-Packard Company Datenkodierung
US6097320A (en) * 1998-01-20 2000-08-01 Silicon Systems, Inc. Encoder/decoder system with suppressed error propagation
US6184806B1 (en) * 1998-03-13 2001-02-06 Quantum Corporation Rate 32/33 (D=0, K=6) run length limited modulation code having optimized error propagation
US6081210A (en) * 1998-05-13 2000-06-27 Texas Instruments Incorporated Sliding block (rate 8/9) trellis code for magnetic recording
EP1017175B1 (de) * 1998-05-27 2007-07-18 Ntt Mobile Communications Network Inc. Verfahren und Vorrichtung zum Verchachteln einer ersten Bitsequenz in eine zweite Bitsequenz
US6198582B1 (en) * 1998-06-24 2001-03-06 Seagate Technology Llc Efficient run length limited code with short interleaved constraint
US6201485B1 (en) * 1999-07-09 2001-03-13 Quantum Corp. High rate runlength limited codes for 8-bit ECC symbols
US6259384B1 (en) 1999-07-09 2001-07-10 Quantum Corporation High rate runlength limited codes for 10-bit ECC symbols
US6651129B1 (en) * 1999-07-21 2003-11-18 National Semiconductor Corporation Apparatus and method for establishing a data communication interface to control and configure an electronic system with analog and digital circuits
EP1089439A1 (de) * 1999-09-28 2001-04-04 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Verschachteler und Eingangsdatabitverschachtelungsverfahren unter Anwendung von symbolkodierter Speicherung und zusätzlichen Informationen
US6329935B1 (en) * 1999-12-22 2001-12-11 International Business Machines Corporation Temporally separating and re-organizing data using two-stage interleaving and de-interleaving
JP4256559B2 (ja) * 2000-03-13 2009-04-22 富士通株式会社 データ再生方法及び装置
JP2001266500A (ja) * 2000-03-23 2001-09-28 Sony Corp データ記録装置及びデータ記録方法、データ再生装置及びデータ再生方法、並びに、データ記録再生装置及びデータ記録再生方法
US6456208B1 (en) * 2000-06-30 2002-09-24 Marvell International, Ltd. Technique to construct 32/33 and other RLL codes
US6661356B1 (en) 2001-03-05 2003-12-09 Marvell International, Ltd. Method and apparatus for DC-level constrained coding
US7286065B1 (en) 2001-03-05 2007-10-23 Marvell International Ltd. Method and apparatus for DC-level constrained coding
US6809894B2 (en) * 2001-06-29 2004-10-26 Infineon Technologies Ag Method and apparatus for handling end of data processing in a data storage device
US6476737B1 (en) * 2001-11-16 2002-11-05 Lsi Logic Corporation Rate 64/65 (d=0, G=11/I=10) run length limited modulation code
US6985320B2 (en) * 2002-01-02 2006-01-10 International Business Machines Corporation Method and apparatus for encoding data to guarantee isolated transitions in a magnetic recording system
US7116736B2 (en) 2002-01-02 2006-10-03 International Business Machines Corporation Method, system, and program for synchronization and resynchronization of a data stream
WO2003079557A1 (en) * 2002-03-04 2003-09-25 Seagate Technology Llc Error correction coding utilizing numerical base conversion for modulation coding
US6759974B1 (en) * 2003-05-20 2004-07-06 Northrop Grumman Corporation Encoder and decoder for data transfer in superconductor circuits
WO2005020440A1 (en) * 2003-08-13 2005-03-03 Seagate Technology Llc Dc-free code design with increased distance between code words
US7030789B1 (en) 2004-12-01 2006-04-18 Hitachi Global Storage Technologies Netherlands B.V. Techniques for applying modulation constraints to data using periodically changing symbol mappings
US8139628B1 (en) 2005-01-10 2012-03-20 Marvell International Ltd. Method and device to compensate for baseline wander
US7071851B1 (en) 2005-01-31 2006-07-04 Hitachi Global Storage Technologies Netherlands B.V. Techniques for implementing non-uniform constraints in modulation encoded data
US7064687B1 (en) 2005-01-31 2006-06-20 Hitachi Global Storage Technologies Netherlands B.V. Techniques for modulating data using short block encoders
US7142134B2 (en) * 2005-02-01 2006-11-28 Hitachi Global Storage Technologies Netherlands B.V. Techniques for generating modulation codes using running substitutions
US7126502B2 (en) * 2005-02-01 2006-10-24 Hitachi Global Storage Technologies Netherlands B.V. Techniques for using interleaved encoders to obtain modulation constraints
KR101355633B1 (ko) * 2007-11-06 2014-01-29 삼성전자주식회사 인코더 및 인코딩 방법
KR20120098105A (ko) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 데이터 전송 회로 및 이를 포함하는 메모리 장치
US10026464B2 (en) * 2016-09-06 2018-07-17 Smart IOPS, Inc. Devices, systems, and methods for increasing the usable life of a storage system by optimizing the energy of stored data

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NL8203110A (nl) * 1982-08-05 1984-03-01 Philips Nv Vierde-orde digitaal multiplex systeem voor transmissie van een aantal digitale signalen met een nominale bitsnelheid van 44 736 kbit/s.
US4802152A (en) * 1986-04-07 1989-01-31 U.S. Philips Corporation Compact disc drive apparatus having an interface for transferring data and commands to and from a host controller
US4707681A (en) * 1986-04-24 1987-11-17 International Business Machines Corporation Method and apparatus for implementing optimum PRML codes
US5109385A (en) * 1989-04-27 1992-04-28 International Business Machines Corporation Enhanced data formats and machine operations for enabling error correction
US5241546A (en) * 1991-02-01 1993-08-31 Quantum Corporation On-the-fly error correction with embedded digital controller
EP0480115A1 (de) * 1990-10-09 1992-04-15 International Business Machines Corporation Verfahren zur Datenkomprimierung und Datenkodierung und Einrichtung zur Durchführung dieses Verfahrens
US5422895A (en) * 1992-01-09 1995-06-06 Quantum Corporation Cross-checking for on-the-fly Reed Solomon error correction code
US5392299A (en) * 1992-01-15 1995-02-21 E-Systems, Inc. Triple orthogonally interleaed error correction system
US5341249A (en) * 1992-08-27 1994-08-23 Quantum Corporation Disk drive using PRML class IV sampling data detection with digital adaptive equalization
US5260703A (en) * 1992-08-27 1993-11-09 Quantum Corporation Data encoding and decoding within PRML class IV sampling data detection channel of disk drive
JPH0778418A (ja) * 1993-09-10 1995-03-20 Matsushita Electric Ind Co Ltd 光ディスク及び光学的記録再生装置
US5537112A (en) * 1994-01-12 1996-07-16 Seagate Technology, Inc. Method and apparatus for implementing run length limited codes in partial response channels
US5576707A (en) * 1994-06-10 1996-11-19 Cirrus Logic, Inc. Method and apparatus for detecting and decoding data in a PRML class-IV digital communication channel
US5635933A (en) * 1995-06-30 1997-06-03 Quantum Corporation Rate 16/17 (d=0,G=6/I=7) modulation code for a magnetic recording channel

Also Published As

Publication number Publication date
EP0846374A1 (de) 1998-06-10
JPH11511610A (ja) 1999-10-05
KR19990044116A (ko) 1999-06-25
EP0846374B1 (de) 2001-03-28
CN1202992A (zh) 1998-12-23
AU7321498A (en) 1998-06-29
WO1997008836A1 (en) 1997-03-06
EP0846374A4 (de) 1998-11-11
DE69612293T2 (de) 2001-10-18
CA2230132A1 (en) 1997-03-06
US5757822A (en) 1998-05-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee