DE69534114D1 - Eine Abtastverriegelungszelle und Testverfahren dafür - Google Patents
Eine Abtastverriegelungszelle und Testverfahren dafürInfo
- Publication number
- DE69534114D1 DE69534114D1 DE69534114T DE69534114T DE69534114D1 DE 69534114 D1 DE69534114 D1 DE 69534114D1 DE 69534114 T DE69534114 T DE 69534114T DE 69534114 T DE69534114 T DE 69534114T DE 69534114 D1 DE69534114 D1 DE 69534114D1
- Authority
- DE
- Germany
- Prior art keywords
- test method
- method therefor
- lock cell
- sample lock
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9421977A GB9421977D0 (en) | 1994-10-31 | 1994-10-31 | A scan latch and test method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69534114D1 true DE69534114D1 (de) | 2005-05-04 |
Family
ID=10763694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69534114T Expired - Lifetime DE69534114D1 (de) | 1994-10-31 | 1995-10-24 | Eine Abtastverriegelungszelle und Testverfahren dafür |
Country Status (5)
Country | Link |
---|---|
US (1) | US5774473A (de) |
EP (1) | EP0709688B1 (de) |
JP (1) | JP2756936B2 (de) |
DE (1) | DE69534114D1 (de) |
GB (1) | GB9421977D0 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872796A (en) * | 1997-06-30 | 1999-02-16 | Sun Microsystems, Inc. | Method for interfacing boundary-scan circuitry with linearized impedance control type output drivers |
GB9810512D0 (en) | 1998-05-15 | 1998-07-15 | Sgs Thomson Microelectronics | Detecting communication errors across a chip boundary |
US6128758A (en) * | 1998-05-20 | 2000-10-03 | National Semiconductor Corporation | Modular re-useable bus architecture |
US6389566B1 (en) | 1998-06-02 | 2002-05-14 | S3 Incorporated | Edge-triggered scan flip-flop and one-pass scan synthesis methodology |
US6341092B1 (en) * | 2000-12-11 | 2002-01-22 | Lsi Logic Corporation | Designing memory for testability to support scan capability in an asic design |
US6920597B2 (en) * | 2002-07-31 | 2005-07-19 | Thomas Hans Rinderknecht | Uniform testing of tristate nets in logic BIST |
US7437634B2 (en) * | 2003-05-13 | 2008-10-14 | Intel Corporation | Test scan cells |
EP1992955B1 (de) | 2003-12-17 | 2012-07-25 | STMicroelectronics (Research & Development) Limited | TAP-Multiplexer |
US7328385B2 (en) * | 2004-08-05 | 2008-02-05 | Seagate Technology Llc | Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements |
KR100604904B1 (ko) * | 2004-10-02 | 2006-07-28 | 삼성전자주식회사 | 스캔 입력을 갖는 플립 플롭 회로 |
US7146551B2 (en) * | 2005-01-20 | 2006-12-05 | Hewlett-Packard Development Company, L.P. | Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof |
US7281182B2 (en) * | 2005-02-22 | 2007-10-09 | International Business Machines Corporation | Method and circuit using boundary scan cells for design library analysis |
JP2006339948A (ja) * | 2005-06-01 | 2006-12-14 | Renesas Technology Corp | パルスラッチ回路及び半導体集積回路 |
US7761748B2 (en) * | 2005-06-09 | 2010-07-20 | Sony Computer Entertainment Inc. | Methods and apparatus for managing clock skew between clock domain boundaries |
US8732499B2 (en) * | 2011-05-27 | 2014-05-20 | Arm Limited | State retention circuit adapted to allow its state integrity to be verified |
US9196329B1 (en) * | 2012-11-29 | 2015-11-24 | Marvell Israel (M.I.S.L) Ltd. | Combinatorial flip flop with off-path scan multiplexer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NO843375L (no) * | 1983-10-06 | 1985-04-09 | Honeywell Inf Systems | Databehandlingssystem og fremgangsmaate til vedlikehold samt anrodning |
US4742293A (en) * | 1987-04-06 | 1988-05-03 | Hughes Aircraft Company | Pseudo-memory circuit for testing for stuck open faults |
US5015875A (en) * | 1989-12-01 | 1991-05-14 | Motorola, Inc. | Toggle-free scan flip-flop |
JP2561164B2 (ja) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | 半導体集積回路 |
-
1994
- 1994-10-31 GB GB9421977A patent/GB9421977D0/en active Pending
-
1995
- 1995-10-24 EP EP95307568A patent/EP0709688B1/de not_active Expired - Lifetime
- 1995-10-24 DE DE69534114T patent/DE69534114D1/de not_active Expired - Lifetime
- 1995-10-30 US US08/558,595 patent/US5774473A/en not_active Expired - Lifetime
- 1995-10-31 JP JP7283678A patent/JP2756936B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5774473A (en) | 1998-06-30 |
JP2756936B2 (ja) | 1998-05-25 |
EP0709688A1 (de) | 1996-05-01 |
EP0709688B1 (de) | 2005-03-30 |
JPH08304511A (ja) | 1996-11-22 |
GB9421977D0 (en) | 1994-12-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |