DE69531092D1 - Einseitige Simplex-Zweitorspeicherzelle - Google Patents

Einseitige Simplex-Zweitorspeicherzelle

Info

Publication number
DE69531092D1
DE69531092D1 DE69531092T DE69531092T DE69531092D1 DE 69531092 D1 DE69531092 D1 DE 69531092D1 DE 69531092 T DE69531092 T DE 69531092T DE 69531092 T DE69531092 T DE 69531092T DE 69531092 D1 DE69531092 D1 DE 69531092D1
Authority
DE
Germany
Prior art keywords
simplex
sided
memory cell
port memory
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69531092T
Other languages
English (en)
Other versions
DE69531092T2 (de
Inventor
Stefan P Sywyk
Richard K Chou
Andrew L Hawkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Application granted granted Critical
Publication of DE69531092D1 publication Critical patent/DE69531092D1/de
Publication of DE69531092T2 publication Critical patent/DE69531092T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69531092T 1994-12-22 1995-10-30 Einseitige Simplex-Zweitorspeicherzelle Expired - Fee Related DE69531092T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US362814 1982-03-29
US36281494A 1994-12-22 1994-12-22

Publications (2)

Publication Number Publication Date
DE69531092D1 true DE69531092D1 (de) 2003-07-24
DE69531092T2 DE69531092T2 (de) 2004-04-01

Family

ID=23427644

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69531092T Expired - Fee Related DE69531092T2 (de) 1994-12-22 1995-10-30 Einseitige Simplex-Zweitorspeicherzelle

Country Status (4)

Country Link
US (2) US6005796A (de)
EP (1) EP0718846B1 (de)
JP (1) JPH08236644A (de)
DE (1) DE69531092T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467017B1 (en) * 1998-06-23 2002-10-15 Altera Corporation Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6731566B1 (en) * 1999-11-18 2004-05-04 Cypress Semiconductor Corporation Single ended simplex dual port memory cell
US6181621B1 (en) * 1999-12-10 2001-01-30 Cypress Semiconductor Corp. Threshold voltage mismatch compensated sense amplifier for SRAM memory arrays
US6240009B1 (en) * 2000-02-02 2001-05-29 Hewlett-Packard Company Asymmetric ram cell
US6747485B1 (en) * 2000-06-28 2004-06-08 Sun Microsystems, Inc. Sense amplifier type input receiver with improved clk to Q
JP2002109885A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体記憶装置
US6751151B2 (en) * 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US6449200B1 (en) 2001-07-17 2002-09-10 International Business Machines Corporation Duty-cycle-efficient SRAM cell test
US6654277B1 (en) * 2002-05-14 2003-11-25 International Business Machines Corp. SRAM with improved noise sensitivity
US7738496B1 (en) 2002-12-31 2010-06-15 Cypress Semiconductor Corporation Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
US6845059B1 (en) * 2003-06-26 2005-01-18 International Business Machines Corporation High performance gain cell architecture
US7158402B2 (en) * 2003-08-06 2007-01-02 Texas Instruments Incorporated Asymmetric static random access memory device having reduced bit line leakage
US6853579B1 (en) * 2003-09-09 2005-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Non-refresh four-transistor memory cell
US7113445B1 (en) 2003-09-26 2006-09-26 Cypress Semiconductor Corporation Multi-port memory cell and access method
US7934057B1 (en) 2003-12-24 2011-04-26 Cypress Semiconductor Corporation Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs
US7483332B2 (en) * 2005-08-11 2009-01-27 Texas Instruments Incorporated SRAM cell using separate read and write circuitry
JP2007234073A (ja) * 2006-02-27 2007-09-13 Fujitsu Ltd 半導体記憶装置
EP2036262A1 (de) * 2006-06-20 2009-03-18 Freescale Semiconductor, Inc. Verfahren zum senden eines datenelements aus einem zeitabhängigen datenspeichermittel
US8001309B2 (en) * 2006-06-22 2011-08-16 Freescale Semiconductor, Inc. Method and system for grouping interrupts from a time-dependent data storage system
US7839697B2 (en) * 2006-12-21 2010-11-23 Panasonic Corporation Semiconductor memory device
US8589632B1 (en) 2007-03-09 2013-11-19 Cypress Semiconductor Corporation Arbitration method for programmable multiple clock domain bi-directional interface
US8145809B1 (en) 2007-03-09 2012-03-27 Cypress Semiconductor Corporation Busy detection logic for asynchronous communication port
US7894280B2 (en) * 2007-10-31 2011-02-22 Texas Instruments Incorporated Asymmetrical SRAM cell with separate word lines
US7859921B2 (en) * 2008-06-09 2010-12-28 International Business Machines Corporation Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines
US7830727B2 (en) * 2008-06-09 2010-11-09 International Business Machines Corporation Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines
US8189368B2 (en) * 2009-07-31 2012-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8009463B2 (en) * 2009-07-31 2011-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8339893B2 (en) * 2009-09-25 2012-12-25 International Business Machines Corporation Dual beta ratio SRAM
US8576655B2 (en) 2011-06-21 2013-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memories
US9058860B2 (en) * 2012-03-29 2015-06-16 Memoir Systems, Inc. Methods and apparatus for synthesizing multi-port memory circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428574A (en) * 1988-12-05 1995-06-27 Motorola, Inc. Static RAM with test features
DE68922738T2 (de) * 1989-12-23 1996-01-25 Ibm Hochintegrierter Halbleiterspeicher mit Mehrfachzugang.
US5289432A (en) * 1991-04-24 1994-02-22 International Business Machines Corporation Dual-port static random access memory cell
JPH05151778A (ja) * 1991-06-05 1993-06-18 Mitsubishi Electric Corp スタテイツクランダムアクセスメモリおよびその制御方法
US5434818A (en) * 1993-12-23 1995-07-18 Unisys Corporation Four port RAM cell
US6072715A (en) * 1994-07-22 2000-06-06 Texas Instruments Incorporated Memory circuit and method of construction

Also Published As

Publication number Publication date
DE69531092T2 (de) 2004-04-01
EP0718846B1 (de) 2003-06-18
EP0718846A3 (de) 1997-07-02
US6005796A (en) 1999-12-21
EP0718846A2 (de) 1996-06-26
US6262912B1 (en) 2001-07-17
JPH08236644A (ja) 1996-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee