DE69530949D1 - Vorrichtung und Verfahren zum Testen eines Systems unter Verwendung eines JTAG-Schaltkreises - Google Patents

Vorrichtung und Verfahren zum Testen eines Systems unter Verwendung eines JTAG-Schaltkreises

Info

Publication number
DE69530949D1
DE69530949D1 DE69530949T DE69530949T DE69530949D1 DE 69530949 D1 DE69530949 D1 DE 69530949D1 DE 69530949 T DE69530949 T DE 69530949T DE 69530949 T DE69530949 T DE 69530949T DE 69530949 D1 DE69530949 D1 DE 69530949D1
Authority
DE
Germany
Prior art keywords
testing
jtag circuit
jtag
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69530949T
Other languages
English (en)
Other versions
DE69530949T2 (de
Inventor
Kayoko Kawano
Yasushi Takaki
Shinichi Sutou
Kazuhiro Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69530949D1 publication Critical patent/DE69530949D1/de
Application granted granted Critical
Publication of DE69530949T2 publication Critical patent/DE69530949T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69530949T 1994-03-17 1995-03-08 Vorrichtung und Verfahren zum Testen eines Systems unter Verwendung eines JTAG-Schaltkreises Expired - Lifetime DE69530949T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4670694 1994-03-17
JP04670694A JP3333036B2 (ja) 1994-03-17 1994-03-17 試験装置、試験装置を備えたシステムおよび試験方法

Publications (2)

Publication Number Publication Date
DE69530949D1 true DE69530949D1 (de) 2003-07-10
DE69530949T2 DE69530949T2 (de) 2004-05-13

Family

ID=12754814

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69530949T Expired - Lifetime DE69530949T2 (de) 1994-03-17 1995-03-08 Vorrichtung und Verfahren zum Testen eines Systems unter Verwendung eines JTAG-Schaltkreises

Country Status (4)

Country Link
US (1) US5781560A (de)
EP (1) EP0672910B1 (de)
JP (1) JP3333036B2 (de)
DE (1) DE69530949T2 (de)

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US6324614B1 (en) * 1997-08-26 2001-11-27 Lee D. Whetsel Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data
US5949272A (en) * 1997-06-12 1999-09-07 International Business Machines Corporation Bidirectional off-chip driver with receiver bypass
US5920765A (en) * 1997-12-12 1999-07-06 Naum; Michael IC wafer-probe testable flip-chip architecture
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6181004B1 (en) 1999-01-22 2001-01-30 Jerry D. Koontz Digital signal processing assembly and test method
US6834356B1 (en) 2000-02-15 2004-12-21 International Business Machines Corporation Functional clock generation controlled by JTAG extensions
US6754863B1 (en) * 2000-04-04 2004-06-22 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6813739B1 (en) * 2000-04-04 2004-11-02 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6760876B1 (en) * 2000-04-04 2004-07-06 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6804802B1 (en) * 2000-06-22 2004-10-12 Cypress Semiconductor Corp. JTAG instruction register and decoder for PLDS
GB2370364B (en) * 2000-12-22 2004-06-30 Advanced Risc Mach Ltd Testing integrated circuits
KR100410554B1 (ko) * 2001-07-13 2003-12-18 삼성전자주식회사 반도체 메모리 장치에서의 패키지 맵 정보 출력방법 및그에 따른 회로
JP2003035751A (ja) * 2001-07-25 2003-02-07 Mitsubishi Electric Corp 半導体集積回路の試験装置及び試験方法
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US7216276B1 (en) 2003-02-27 2007-05-08 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7496818B1 (en) 2003-02-27 2009-02-24 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7444571B1 (en) 2003-02-27 2008-10-28 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
CN100427964C (zh) * 2003-08-04 2008-10-22 华为技术有限公司 一种电路板的边界扫描测试方法
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
CN101292171B (zh) * 2005-10-24 2012-04-18 Nxp股份有限公司 Ic测试方法和设备
KR100707297B1 (ko) 2005-12-01 2007-04-12 (주)알파칩스 시스템 버스를 이용한 제이티에이지 테스트 장치
KR100715492B1 (ko) * 2006-06-05 2007-05-07 (주)엠씨티코리아 극미세 피치를 갖는 프로브유니트 및 이를 이용한프로브장치
US8037252B2 (en) * 2007-08-28 2011-10-11 International Business Machines Corporation Method for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor
US9274174B2 (en) * 2013-08-29 2016-03-01 Lenovo (Singapore) Pte. Ltd. Processor TAP support for remote services
US20150106660A1 (en) * 2013-10-16 2015-04-16 Lenovo (Singapore) Pte. Ltd. Controller access to host memory
US9810739B2 (en) * 2015-10-27 2017-11-07 Andes Technology Corporation Electronic system, system diagnostic circuit and operation method thereof
US10746798B1 (en) 2019-05-31 2020-08-18 Nvidia Corp. Field adaptable in-system test mechanisms
US11204849B2 (en) * 2020-03-13 2021-12-21 Nvidia Corporation Leveraging low power states for fault testing of processing cores at runtime

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Publication number Priority date Publication date Assignee Title
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US5115435A (en) * 1989-10-19 1992-05-19 Ncr Corporation Method and apparatus for bus executed boundary scanning
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG
GB9115097D0 (en) * 1991-07-12 1991-08-28 Motorola Inc Microcomputer with boundary-scan facility
US5343478A (en) * 1991-11-27 1994-08-30 Ncr Corporation Computer system configuration via test bus
US5452419A (en) * 1992-03-06 1995-09-19 Pitney Bowes Inc. Serial communication control system between nodes having predetermined intervals for synchronous communications and mediating asynchronous communications for unused time in the predetermined intervals
US5400345A (en) * 1992-03-06 1995-03-21 Pitney Bowes Inc. Communications system to boundary-scan logic interface
US5341380A (en) * 1992-03-19 1994-08-23 Nec Corporation Large-scale integrated circuit device
US5285152A (en) * 1992-03-23 1994-02-08 Ministar Peripherals International Limited Apparatus and methods for testing circuit board interconnect integrity
EP0570067B1 (de) * 1992-05-11 2001-08-08 Jtag Technologies B.V. Steuerungseinrichtung zur Schnittstellensteuerung zwischen einer Testmaschine und einer elektronischen Mehrkanalschaltung, insbesondere nach dem "Boundary Test Standard"
FI93999C (fi) * 1992-06-11 1995-06-26 Nokia Mobile Phones Ltd Piirikortille asennetun mikroprosessorin ohjelmamuistin ohjelmoiminen
US5450415A (en) * 1992-11-25 1995-09-12 Matsushita Electric Industrial Co., Ltd. Boundary scan cell circuit and boundary scan test circuit

Also Published As

Publication number Publication date
US5781560A (en) 1998-07-14
JP3333036B2 (ja) 2002-10-07
EP0672910B1 (de) 2003-06-04
EP0672910A1 (de) 1995-09-20
JPH07260883A (ja) 1995-10-13
DE69530949T2 (de) 2004-05-13

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