DE69529510T2 - Pipelineprozessor mit reduzierten Verschränkungen, die von Verzweigungsbefehlen veranlasst werden - Google Patents

Pipelineprozessor mit reduzierten Verschränkungen, die von Verzweigungsbefehlen veranlasst werden

Info

Publication number
DE69529510T2
DE69529510T2 DE69529510T DE69529510T DE69529510T2 DE 69529510 T2 DE69529510 T2 DE 69529510T2 DE 69529510 T DE69529510 T DE 69529510T DE 69529510 T DE69529510 T DE 69529510T DE 69529510 T2 DE69529510 T2 DE 69529510T2
Authority
DE
Germany
Prior art keywords
reduced
branch instructions
pipeline processor
entanglements
caused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69529510T
Other languages
English (en)
Other versions
DE69529510D1 (de
Inventor
Masato Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69529510D1 publication Critical patent/DE69529510D1/de
Publication of DE69529510T2 publication Critical patent/DE69529510T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
DE69529510T 1994-12-06 1995-11-29 Pipelineprozessor mit reduzierten Verschränkungen, die von Verzweigungsbefehlen veranlasst werden Expired - Lifetime DE69529510T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30182894A JP3504355B2 (ja) 1994-12-06 1994-12-06 プロセッサ

Publications (2)

Publication Number Publication Date
DE69529510D1 DE69529510D1 (de) 2003-03-06
DE69529510T2 true DE69529510T2 (de) 2003-06-26

Family

ID=17901655

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69529510T Expired - Lifetime DE69529510T2 (de) 1994-12-06 1995-11-29 Pipelineprozessor mit reduzierten Verschränkungen, die von Verzweigungsbefehlen veranlasst werden

Country Status (4)

Country Link
US (1) US5729727A (de)
EP (1) EP0716376B1 (de)
JP (1) JP3504355B2 (de)
DE (1) DE69529510T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3526773B2 (ja) * 1999-02-26 2004-05-17 松下電器産業株式会社 マルチプロセッサ装置およびその制御方法
US6622240B1 (en) * 1999-06-18 2003-09-16 Intrinsity, Inc. Method and apparatus for pre-branch instruction
US7278014B2 (en) * 2004-12-02 2007-10-02 International Business Machines Corporation System and method for simulating hardware interrupts
JP2007041837A (ja) * 2005-08-03 2007-02-15 Nec Electronics Corp 命令プリフェッチ装置及び命令プリフェッチ方法
US7478228B2 (en) * 2006-08-31 2009-01-13 Qualcomm Incorporated Apparatus for generating return address predictions for implicit and explicit subroutine calls

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5592947A (en) * 1978-12-29 1980-07-14 Fujitsu Ltd Interruption control system for microprogram
JPS573142A (en) * 1980-06-04 1982-01-08 Matsushita Electric Ind Co Ltd Instruction prefetching system
US4488227A (en) * 1982-12-03 1984-12-11 Honeywell Information Systems Inc. Program counter stacking method and apparatus for nested subroutines and interrupts
US4654786A (en) * 1984-04-11 1987-03-31 Texas Instruments Incorporated Data processor using picosquencer to control execution of multi-instruction subroutines in a single fetch cycle
JPS62226232A (ja) * 1986-03-28 1987-10-05 Toshiba Corp 分岐先アドレス算出回路
JPS63317828A (ja) * 1987-06-19 1988-12-26 Fujitsu Ltd マイクロコ−ド読み出し制御方式
KR970005453B1 (ko) * 1987-12-25 1997-04-16 가부시기가이샤 히다찌세이사꾸쇼 고속처리에 적합한 데이타 처리장치
US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
US5099419A (en) * 1988-11-25 1992-03-24 Nec Corporation Pipeline microcomputer having branch instruction detector and bus controller for producing and carrying branch destination address prior to instruction execution
US5034880A (en) * 1988-12-22 1991-07-23 Wang Laboratories, Inc. Apparatus and method for executing a conditional branch instruction
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
JP3555900B2 (ja) * 1993-08-26 2004-08-18 日本化薬株式会社 水面拡散型固形農薬製剤

Also Published As

Publication number Publication date
DE69529510D1 (de) 2003-03-06
US5729727A (en) 1998-03-17
JPH08161166A (ja) 1996-06-21
EP0716376B1 (de) 2003-01-29
EP0716376A2 (de) 1996-06-12
JP3504355B2 (ja) 2004-03-08
EP0716376A3 (de) 1998-04-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8320 Willingness to grant licences declared (paragraph 23)