DE69518118D1 - Integrierte Halbleiterschaltung mit einer SRAM-Zellenmatrix mit einseitiger Stromabfühlschaltung - Google Patents

Integrierte Halbleiterschaltung mit einer SRAM-Zellenmatrix mit einseitiger Stromabfühlschaltung

Info

Publication number
DE69518118D1
DE69518118D1 DE69518118T DE69518118T DE69518118D1 DE 69518118 D1 DE69518118 D1 DE 69518118D1 DE 69518118 T DE69518118 T DE 69518118T DE 69518118 T DE69518118 T DE 69518118T DE 69518118 D1 DE69518118 D1 DE 69518118D1
Authority
DE
Germany
Prior art keywords
current sensing
sram cell
integrated semiconductor
circuit
cell matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69518118T
Other languages
English (en)
Other versions
DE69518118T2 (de
Inventor
Kevin John O'connor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69518118D1 publication Critical patent/DE69518118D1/de
Publication of DE69518118T2 publication Critical patent/DE69518118T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Measuring Magnetic Variables (AREA)
DE69518118T 1994-05-27 1995-05-17 Integrierte Halbleiterschaltung mit einer SRAM-Zellenmatrix mit einseitiger Stromabfühlschaltung Expired - Fee Related DE69518118T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25074694A 1994-05-27 1994-05-27

Publications (2)

Publication Number Publication Date
DE69518118D1 true DE69518118D1 (de) 2000-08-31
DE69518118T2 DE69518118T2 (de) 2001-05-31

Family

ID=22948969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518118T Expired - Fee Related DE69518118T2 (de) 1994-05-27 1995-05-17 Integrierte Halbleiterschaltung mit einer SRAM-Zellenmatrix mit einseitiger Stromabfühlschaltung

Country Status (5)

Country Link
US (1) US5541874A (de)
EP (1) EP0685850B1 (de)
JP (1) JP3349293B2 (de)
KR (1) KR950034798A (de)
DE (1) DE69518118T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850359A (en) * 1996-10-29 1998-12-15 V.L.S.I. Technology, Inc. Asynchronous high speed zero DC-current SRAM system
US5847990A (en) * 1996-12-23 1998-12-08 Lsi Logic Corporation Ram cell capable of storing 3 logic states
FR2767412B1 (fr) * 1997-08-14 2000-06-16 Dolphin Integration Sa Cellule memoire a lecture en courant
US6751151B2 (en) * 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US7054217B2 (en) * 2003-09-12 2006-05-30 Sanyo Electric Co. Ltd. Semiconductor memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321658A (en) * 1990-05-31 1994-06-14 Oki Electric Industry Co., Ltd. Semiconductor memory device being coupled by auxiliary power lines to a main power line
US5282174A (en) * 1992-01-31 1994-01-25 At&T Bell Laboratories Dual-port memory with read and read/write ports
US5265047A (en) * 1992-03-09 1993-11-23 Monolithic System Technology High density SRAM circuit with single-ended memory cells
EP0578915A3 (en) * 1992-07-16 1994-05-18 Hewlett Packard Co Two-port ram cell

Also Published As

Publication number Publication date
DE69518118T2 (de) 2001-05-31
US5541874A (en) 1996-07-30
KR950034798A (ko) 1995-12-28
JP3349293B2 (ja) 2002-11-20
JPH07335838A (ja) 1995-12-22
EP0685850A3 (de) 1995-12-20
EP0685850A2 (de) 1995-12-06
EP0685850B1 (de) 2000-07-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee