DE69516865D1 - Matrixarchitektur mit verbesserter leitweglenkung für lineare asics - Google Patents

Matrixarchitektur mit verbesserter leitweglenkung für lineare asics

Info

Publication number
DE69516865D1
DE69516865D1 DE69516865T DE69516865T DE69516865D1 DE 69516865 D1 DE69516865 D1 DE 69516865D1 DE 69516865 T DE69516865 T DE 69516865T DE 69516865 T DE69516865 T DE 69516865T DE 69516865 D1 DE69516865 D1 DE 69516865D1
Authority
DE
Germany
Prior art keywords
asics
linear
improved guide
matrix architecture
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69516865T
Other languages
English (en)
Other versions
DE69516865T2 (de
Inventor
J Male
Douglas L Anneser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Technologies Corp
Original Assignee
United Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Technologies Corp filed Critical United Technologies Corp
Application granted granted Critical
Publication of DE69516865D1 publication Critical patent/DE69516865D1/de
Publication of DE69516865T2 publication Critical patent/DE69516865T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
DE69516865T 1994-04-01 1995-03-30 Matrixarchitektur mit verbesserter leitweglenkung für lineare asics Expired - Fee Related DE69516865T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/222,736 US5440153A (en) 1994-04-01 1994-04-01 Array architecture with enhanced routing for linear asics
PCT/US1995/004053 WO1995027311A1 (en) 1994-04-01 1995-03-30 ARRAY ARCHITECTURE WITH ENHANCED ROUTING FOR LINEAR ASICs

Publications (2)

Publication Number Publication Date
DE69516865D1 true DE69516865D1 (de) 2000-06-15
DE69516865T2 DE69516865T2 (de) 2000-10-12

Family

ID=22833465

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69516865T Expired - Fee Related DE69516865T2 (de) 1994-04-01 1995-03-30 Matrixarchitektur mit verbesserter leitweglenkung für lineare asics

Country Status (5)

Country Link
US (1) US5440153A (de)
EP (1) EP0754352B1 (de)
JP (1) JPH09511363A (de)
DE (1) DE69516865T2 (de)
WO (1) WO1995027311A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5659189A (en) * 1995-06-07 1997-08-19 Lsi Logic Corporation Layout configuration for an integrated circuit gate array
US5708288A (en) * 1995-11-02 1998-01-13 Motorola, Inc. Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method
JP3152145B2 (ja) * 1996-02-28 2001-04-03 日本電気株式会社 半導体装置
US5783963A (en) * 1996-02-29 1998-07-21 Lexmark International, Inc. ASIC with selectable output drivers
US6462977B2 (en) 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
US7283381B2 (en) 2000-08-17 2007-10-16 David Earl Butz System and methods for addressing a matrix incorporating virtual columns and addressing layers
US6756963B2 (en) * 2001-09-28 2004-06-29 Three-Five Systems, Inc. High contrast LCD microdisplay
US7989917B2 (en) * 2002-01-31 2011-08-02 Nxp B.V. Integrated circuit device including a resistor having a narrow-tolerance resistance value coupled to an active component
US20090182229A1 (en) * 2008-01-10 2009-07-16 Robert Gideon Wodnicki UltraSound System With Highly Integrated ASIC Architecture
DE102008064046A1 (de) * 2008-10-02 2010-04-08 Continental Teves Ag & Co. Ohg Verfahren zur Herstellung eines Geschwindigkeits-Sensorelementes
DE102008064047A1 (de) * 2008-10-02 2010-04-08 Continental Teves Ag & Co. Ohg Sensorelement und Trägerelement zur Herstellung eines Sensors
US8431968B2 (en) 2010-07-28 2013-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Electromigration resistant standard cell device

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
NL176029C (nl) * 1973-02-01 1985-02-01 Philips Nv Geintegreerde logische schakeling met komplementaire transistoren.
JPS57160145A (en) * 1981-03-27 1982-10-02 Fujitsu Ltd Manufacture of semiconductor integrated circuit
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
JPS58166742A (ja) * 1982-03-29 1983-10-01 Nec Corp マスタ−スライス基板
EP0131463B1 (de) * 1983-07-09 1989-03-15 Fujitsu Limited "Master-slice"-Halbleiteranordnung
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS60101951A (ja) * 1983-11-08 1985-06-06 Sanyo Electric Co Ltd ゲ−トアレイ
US4623911A (en) * 1983-12-16 1986-11-18 Rca Corporation High circuit density ICs
US4745084A (en) * 1986-11-12 1988-05-17 Vlsi Technology, Inc. Method of making a customized semiconductor integrated device
US4851893A (en) * 1987-11-19 1989-07-25 Exar Corporation Programmable active/passive cell structure
JP2692099B2 (ja) * 1988-01-14 1997-12-17 日本電気株式会社 マスタースライス方式の集積回路
EP0382415B1 (de) * 1989-02-09 1994-09-28 Sony Corporation Integrierte Halbleiterschaltungsanordnungen
JP2632420B2 (ja) * 1989-02-23 1997-07-23 三菱電機株式会社 半導体集積回路
JPH0329342A (ja) * 1989-06-26 1991-02-07 Toshiba Corp 半導体装置
US4978633A (en) * 1989-08-22 1990-12-18 Harris Corporation Hierarchical variable die size gate array architecture
JPH0434973A (ja) * 1990-05-30 1992-02-05 Toshiba Corp 半導体基板
US5063429A (en) * 1990-09-17 1991-11-05 Ncr Corporation High density input/output cell arrangement for integrated circuits

Also Published As

Publication number Publication date
EP0754352A1 (de) 1997-01-22
US5440153A (en) 1995-08-08
JPH09511363A (ja) 1997-11-11
EP0754352B1 (de) 2000-05-10
WO1995027311A1 (en) 1995-10-12
DE69516865T2 (de) 2000-10-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee