DE69430744T2 - Verbesserte Neuronalhalbleiterchipsarchitekturen und Neuronalnetzwerke darin - Google Patents

Verbesserte Neuronalhalbleiterchipsarchitekturen und Neuronalnetzwerke darin

Info

Publication number
DE69430744T2
DE69430744T2 DE69430744T DE69430744T DE69430744T2 DE 69430744 T2 DE69430744 T2 DE 69430744T2 DE 69430744 T DE69430744 T DE 69430744T DE 69430744 T DE69430744 T DE 69430744T DE 69430744 T2 DE69430744 T2 DE 69430744T2
Authority
DE
Germany
Prior art keywords
neural
semiconductor chip
improved
chip architectures
neural networks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430744T
Other languages
English (en)
Other versions
DE69430744D1 (de
Inventor
Andre Steimle
Guy Paillet
Pascal Tannhof
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69430744D1 publication Critical patent/DE69430744D1/de
Publication of DE69430744T2 publication Critical patent/DE69430744T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/24—Classification techniques
    • G06F18/241—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
    • G06F18/2413—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on distances to training or reference patterns
    • G06F18/24133—Distances to prototypes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/764—Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
    • G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
DE69430744T 1994-07-28 1994-07-28 Verbesserte Neuronalhalbleiterchipsarchitekturen und Neuronalnetzwerke darin Expired - Fee Related DE69430744T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94480070A EP0694854B1 (de) 1994-07-28 1994-07-28 Verbesserte Neuronalhalbleiterchipsarchitekturen und Neuronalnetzwerke darin

Publications (2)

Publication Number Publication Date
DE69430744D1 DE69430744D1 (de) 2002-07-11
DE69430744T2 true DE69430744T2 (de) 2003-01-30

Family

ID=8218126

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430744T Expired - Fee Related DE69430744T2 (de) 1994-07-28 1994-07-28 Verbesserte Neuronalhalbleiterchipsarchitekturen und Neuronalnetzwerke darin

Country Status (5)

Country Link
US (1) US5717832A (de)
EP (1) EP0694854B1 (de)
JP (1) JP3407266B2 (de)
CA (1) CA2149479C (de)
DE (1) DE69430744T2 (de)

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Also Published As

Publication number Publication date
JPH08171540A (ja) 1996-07-02
EP0694854A1 (de) 1996-01-31
JP3407266B2 (ja) 2003-05-19
EP0694854B1 (de) 2002-06-05
CA2149479A1 (en) 1996-01-29
US5717832A (en) 1998-02-10
DE69430744D1 (de) 2002-07-11
CA2149479C (en) 2001-05-15

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Legal Events

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8339 Ceased/non-payment of the annual fee