DE69430551D1 - Halbleitervorrichtung zur Reduzierung einer Taktverschiebung in einer Vielfalt von Mustern von Verdrahtungsblöcken - Google Patents

Halbleitervorrichtung zur Reduzierung einer Taktverschiebung in einer Vielfalt von Mustern von Verdrahtungsblöcken

Info

Publication number
DE69430551D1
DE69430551D1 DE69430551T DE69430551T DE69430551D1 DE 69430551 D1 DE69430551 D1 DE 69430551D1 DE 69430551 T DE69430551 T DE 69430551T DE 69430551 T DE69430551 T DE 69430551T DE 69430551 D1 DE69430551 D1 DE 69430551D1
Authority
DE
Germany
Prior art keywords
variety
semiconductor device
clock skew
wiring block
block patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430551T
Other languages
English (en)
Other versions
DE69430551T2 (de
Inventor
Hitoshi Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69430551D1 publication Critical patent/DE69430551D1/de
Publication of DE69430551T2 publication Critical patent/DE69430551T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69430551T 1993-02-15 1994-02-14 Halbleitervorrichtung zur Reduzierung einer Taktverschiebung in einer Vielfalt von Mustern von Verdrahtungsblöcken Expired - Fee Related DE69430551T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5024621A JPH06244282A (ja) 1993-02-15 1993-02-15 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69430551D1 true DE69430551D1 (de) 2002-06-13
DE69430551T2 DE69430551T2 (de) 2003-01-09

Family

ID=12143224

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430551T Expired - Fee Related DE69430551T2 (de) 1993-02-15 1994-02-14 Halbleitervorrichtung zur Reduzierung einer Taktverschiebung in einer Vielfalt von Mustern von Verdrahtungsblöcken

Country Status (4)

Country Link
US (1) US5521541A (de)
EP (1) EP0612151B1 (de)
JP (1) JPH06244282A (de)
DE (1) DE69430551T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714904A (en) * 1994-06-06 1998-02-03 Sun Microsystems, Inc. High speed serial link for fully duplexed data communication
JPH09107048A (ja) * 1995-03-30 1997-04-22 Mitsubishi Electric Corp 半導体パッケージ
JP3434397B2 (ja) 1995-09-06 2003-08-04 三菱電機株式会社 半導体記憶装置
US5656963A (en) * 1995-09-08 1997-08-12 International Business Machines Corporation Clock distribution network for reducing clock skew
US5831459A (en) * 1995-11-13 1998-11-03 International Business Machines Corporation Method and system for adjusting a clock signal within electronic circuitry
US6124744A (en) * 1996-03-26 2000-09-26 Kabushiki Kaisha Toshiba Electronic circuit apparatus having circuits for effectively compensating for clock skew
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US6118334A (en) * 1997-05-19 2000-09-12 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and power supply routing method and system
US5969559A (en) * 1997-06-09 1999-10-19 Schwartz; David M. Method and apparatus for using a power grid for clock distribution in semiconductor integrated circuits
JP3441948B2 (ja) * 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
JP3052925B2 (ja) 1998-02-27 2000-06-19 日本電気株式会社 クロック制御方法および回路
JP2000035832A (ja) * 1998-07-21 2000-02-02 Nec Corp 半導体集積回路及びそのクロック分配方法
JP2000099190A (ja) 1998-09-28 2000-04-07 Nec Corp 信号分配回路および信号線接続方法
JP2000200114A (ja) 1999-01-07 2000-07-18 Nec Corp クロック分配回路
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
US6522186B2 (en) * 2001-06-27 2003-02-18 Intel Corporation Hierarchical clock grid for on-die salphasic clocking
JP3672889B2 (ja) * 2001-08-29 2005-07-20 Ｎｅｃエレクトロニクス株式会社 半導体集積回路とそのレイアウト方法
JP2004286540A (ja) * 2003-03-20 2004-10-14 Matsushita Electric Ind Co Ltd 半導体集積回路
US7679416B2 (en) * 2004-05-24 2010-03-16 The Regents Of The University Of California High speed clock distribution transmission line network
US9349682B2 (en) * 2014-02-27 2016-05-24 Mediatek Inc. Semiconductor chip and semiconductor chip package each having signal paths that balance clock skews

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6369262A (ja) * 1986-09-10 1988-03-29 Hitachi Ltd 半導体集積回路
JPS63107316A (ja) * 1986-10-24 1988-05-12 Nec Corp ゲ−トアレ−のクロツク分配構造
JPH083773B2 (ja) * 1987-02-23 1996-01-17 株式会社日立製作所 大規模半導体論理回路
JPH01289155A (ja) * 1988-05-16 1989-11-21 Matsushita Electric Ind Co Ltd 半導体集積回路
US5239215A (en) * 1988-05-16 1993-08-24 Matsushita Electric Industrial Co., Ltd. Large scale integrated circuit configured to eliminate clock signal skew effects
JP2622612B2 (ja) * 1989-11-14 1997-06-18 三菱電機株式会社 集積回路
JP2756325B2 (ja) * 1989-12-07 1998-05-25 株式会社日立製作所 クロック供給回路
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
US5394490A (en) * 1992-08-11 1995-02-28 Hitachi, Ltd. Semiconductor device having an optical waveguide interposed in the space between electrode members

Also Published As

Publication number Publication date
US5521541A (en) 1996-05-28
JPH06244282A (ja) 1994-09-02
EP0612151A2 (de) 1994-08-24
DE69430551T2 (de) 2003-01-09
EP0612151B1 (de) 2002-05-08
EP0612151A3 (de) 1997-05-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee