DE69428415D1 - Datenbusstruktur für beschleunigten Spaltenzugriff in einem RAM - Google Patents

Datenbusstruktur für beschleunigten Spaltenzugriff in einem RAM

Info

Publication number
DE69428415D1
DE69428415D1 DE69428415T DE69428415T DE69428415D1 DE 69428415 D1 DE69428415 D1 DE 69428415D1 DE 69428415 T DE69428415 T DE 69428415T DE 69428415 T DE69428415 T DE 69428415T DE 69428415 D1 DE69428415 D1 DE 69428415D1
Authority
DE
Germany
Prior art keywords
ram
data bus
bus structure
column access
accelerated column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69428415T
Other languages
English (en)
Other versions
DE69428415T2 (de
Inventor
Allan Graham
Francis Larochelle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Fujitsu Semiconductor Ltd
Original Assignee
Mosaid Technologies Inc
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc, Fujitsu Ltd filed Critical Mosaid Technologies Inc
Publication of DE69428415D1 publication Critical patent/DE69428415D1/de
Application granted granted Critical
Publication of DE69428415T2 publication Critical patent/DE69428415T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69428415T 1993-12-10 1994-12-09 Datenbusstruktur für beschleunigten Spaltenzugriff in einem RAM Expired - Fee Related DE69428415T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/164,703 US5416743A (en) 1993-12-10 1993-12-10 Databus architecture for accelerated column access in RAM

Publications (2)

Publication Number Publication Date
DE69428415D1 true DE69428415D1 (de) 2001-10-31
DE69428415T2 DE69428415T2 (de) 2002-06-20

Family

ID=22595707

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69428415T Expired - Fee Related DE69428415T2 (de) 1993-12-10 1994-12-09 Datenbusstruktur für beschleunigten Spaltenzugriff in einem RAM

Country Status (5)

Country Link
US (1) US5416743A (de)
EP (1) EP0657891B1 (de)
JP (2) JPH07220475A (de)
KR (1) KR100202777B1 (de)
DE (1) DE69428415T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387827A (en) * 1990-01-20 1995-02-07 Hitachi, Ltd. Semiconductor integrated circuit having logic gates
GB2286271B (en) * 1994-01-31 1998-02-18 Advanced Risc Mach Ltd Data memory with sense amplifier
JPH07282582A (ja) * 1994-04-11 1995-10-27 Mitsubishi Electric Corp 半導体記憶装置
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
US5633605A (en) * 1995-05-24 1997-05-27 International Business Machines Corporation Dynamic bus with singular central precharge
JPH0963264A (ja) * 1995-08-18 1997-03-07 Fujitsu Ltd 同期型ｄｒａｍ
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
US5802597A (en) * 1995-12-22 1998-09-01 Cirrus Logic, Inc. SDRAM memory controller while in burst four mode supporting single data accesses
JP3277112B2 (ja) * 1996-01-31 2002-04-22 株式会社東芝 半導体記憶装置
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5680365A (en) * 1996-05-16 1997-10-21 Mitsubishi Semiconductor America, Inc. Shared dram I/O databus for high speed operation
US5745422A (en) * 1996-11-12 1998-04-28 International Business Machines Corporation Cross-coupled bitline segments for generalized data propagation
KR100240418B1 (ko) * 1996-12-31 2000-03-02 윤종용 반도체 독출 전용 메모리 및 그의 독출 방법
US5894238A (en) * 1997-01-28 1999-04-13 Chien; Pien Output buffer with static and transient pull-up and pull-down drivers
JP3244048B2 (ja) * 1998-05-19 2002-01-07 日本電気株式会社 半導体記憶装置
US6279071B1 (en) 1998-07-07 2001-08-21 Mitsubishi Electric And Electronics Usa, Inc. System and method for column access in random access memories
US6356102B1 (en) 1998-11-13 2002-03-12 Integrated Device Technology, Inc. Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals
US6242942B1 (en) 1998-11-13 2001-06-05 Integrated Device Technology, Inc. Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics
US6091260A (en) * 1998-11-13 2000-07-18 Integrated Device Technology, Inc. Integrated circuit output buffers having low propagation delay and improved noise characteristics
KR100365737B1 (ko) * 1998-12-24 2003-02-19 주식회사 하이닉스반도체 안정적인신호전달을위한보조구동회로를갖는반도체소자
KR20010004539A (ko) * 1999-06-29 2001-01-15 김영환 반도체 메모리 소자
US6601123B1 (en) * 1999-12-23 2003-07-29 Intel Corporation Method and apparatus to control the signal development rate of a differential bus
US6373778B1 (en) 2000-01-28 2002-04-16 Mosel Vitelic, Inc. Burst operations in memories
KR100334574B1 (ko) * 2000-01-31 2002-05-03 윤종용 풀-페이지 모드를 갖는 버스트-타입의 반도체 메모리 장치
US6191997B1 (en) 2000-03-10 2001-02-20 Mosel Vitelic Inc. Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.
US20020174290A1 (en) * 2001-05-15 2002-11-21 Wu Kun Ho Memory accelerator, acceleration method and associated interface card and motherboard
US6501688B2 (en) * 2001-05-30 2002-12-31 Micron Technology, Inc. tRCD margin
DE10316581B4 (de) * 2003-04-10 2010-04-22 Qimonda Ag Integrierter Speicher mit einer Spannungsgeneratorschaltung zur Erzeugung einer Spannungsversorgung für einen Schreib-Lese-Verstärker
US7283418B2 (en) * 2005-07-26 2007-10-16 Micron Technology, Inc. Memory device and method having multiple address, data and command buses
US11763880B2 (en) * 2020-03-30 2023-09-19 Arm Limited Column multiplexer circuitry

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128292A (ja) * 1987-11-13 1989-05-19 Sanyo Electric Co Ltd 半導体記憶回路
US5293563A (en) * 1988-12-29 1994-03-08 Sharp Kabushiki Kaisha Multi-level memory cell with increased read-out margin
JP2761515B2 (ja) * 1989-03-08 1998-06-04 株式会社日立製作所 半導体記憶装置
JP2876799B2 (ja) * 1991-03-13 1999-03-31 富士通株式会社 半導体記憶装置
JPH0589676A (ja) * 1991-09-25 1993-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPH05217365A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 半導体記憶装置
JPH1128292A (ja) * 1997-07-09 1999-02-02 Kaneko:Kk ゲーム装置

Also Published As

Publication number Publication date
KR100202777B1 (ko) 1999-06-15
EP0657891A3 (de) 1995-11-22
DE69428415T2 (de) 2002-06-20
EP0657891A2 (de) 1995-06-14
JP4649619B2 (ja) 2011-03-16
EP0657891B1 (de) 2001-09-26
US5416743A (en) 1995-05-16
KR950020729A (ko) 1995-07-24
JPH07220475A (ja) 1995-08-18
JP2007257826A (ja) 2007-10-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

Owner name: MOSAID TECHNOLOGIES INCORPORATED, KANATA, ONTA, CA

8327 Change in the person/name/address of the patent owner

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

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