DE69421738D1 - Halbleiter-Schmelzsicherungstrukturen - Google Patents

Halbleiter-Schmelzsicherungstrukturen

Info

Publication number
DE69421738D1
DE69421738D1 DE69421738T DE69421738T DE69421738D1 DE 69421738 D1 DE69421738 D1 DE 69421738D1 DE 69421738 T DE69421738 T DE 69421738T DE 69421738 T DE69421738 T DE 69421738T DE 69421738 D1 DE69421738 D1 DE 69421738D1
Authority
DE
Germany
Prior art keywords
fuse structures
semiconductor fuse
semiconductor
structures
fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69421738T
Other languages
English (en)
Other versions
DE69421738T2 (de
Inventor
Michael L Grams
Ehren T Achee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69421738D1 publication Critical patent/DE69421738D1/de
Publication of DE69421738T2 publication Critical patent/DE69421738T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE1994621738 1993-04-01 1994-03-22 Halbleiter-Schmelzsicherungstrukturen Expired - Fee Related DE69421738T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4167793A 1993-04-01 1993-04-01

Publications (2)

Publication Number Publication Date
DE69421738D1 true DE69421738D1 (de) 1999-12-30
DE69421738T2 DE69421738T2 (de) 2000-06-29

Family

ID=21917753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1994621738 Expired - Fee Related DE69421738T2 (de) 1993-04-01 1994-03-22 Halbleiter-Schmelzsicherungstrukturen

Country Status (3)

Country Link
EP (1) EP0618620B1 (de)
JP (1) JPH06302699A (de)
DE (1) DE69421738T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650355A (en) * 1995-03-30 1997-07-22 Texas Instruments Incorporated Process of making and process of trimming a fuse in a top level metal and in a step
US6624499B2 (en) * 2002-02-28 2003-09-23 Infineon Technologies Ag System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient
JP2006286723A (ja) * 2005-03-31 2006-10-19 Yamaha Corp 半導体装置および同装置におけるヒューズ素子の切断方法
US7645645B2 (en) * 2006-03-09 2010-01-12 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2625089A1 (de) * 1976-06-04 1977-12-15 Bosch Gmbh Robert Anordnung zum auftrennen von leiterbahnen auf integrierten schaltkreisen
US4209894A (en) * 1978-04-27 1980-07-01 Texas Instruments Incorporated Fusible-link semiconductor memory
JPS6084837A (ja) * 1983-10-17 1985-05-14 Hitachi Ltd 半導体集積回路装置
JPH0719842B2 (ja) * 1985-05-23 1995-03-06 三菱電機株式会社 半導体装置の冗長回路

Also Published As

Publication number Publication date
DE69421738T2 (de) 2000-06-29
JPH06302699A (ja) 1994-10-28
EP0618620B1 (de) 1999-11-24
EP0618620A1 (de) 1994-10-05

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee