DE69420573T2 - Schaltung zur reduzierung von gleichzeitigem transientem leiten - Google Patents

Schaltung zur reduzierung von gleichzeitigem transientem leiten

Info

Publication number
DE69420573T2
DE69420573T2 DE69420573T DE69420573T DE69420573T2 DE 69420573 T2 DE69420573 T2 DE 69420573T2 DE 69420573 T DE69420573 T DE 69420573T DE 69420573 T DE69420573 T DE 69420573T DE 69420573 T2 DE69420573 T2 DE 69420573T2
Authority
DE
Germany
Prior art keywords
conduct
circuit
reduce simultaneous
simultaneous transient
transient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69420573T
Other languages
English (en)
Other versions
DE69420573D1 (de
Inventor
Jeffrey Davis
Jay Chapin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE69420573D1 publication Critical patent/DE69420573D1/de
Application granted granted Critical
Publication of DE69420573T2 publication Critical patent/DE69420573T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE69420573T 1993-09-24 1994-07-19 Schaltung zur reduzierung von gleichzeitigem transientem leiten Expired - Fee Related DE69420573T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/126,914 US5418474A (en) 1993-09-24 1993-09-24 Circuit for reducing transient simultaneous conduction
PCT/US1994/008139 WO1995008871A1 (en) 1993-09-24 1994-07-19 Circuit for reducing transient simultaneous conduction

Publications (2)

Publication Number Publication Date
DE69420573D1 DE69420573D1 (de) 1999-10-14
DE69420573T2 true DE69420573T2 (de) 2000-04-27

Family

ID=22427356

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69420573T Expired - Fee Related DE69420573T2 (de) 1993-09-24 1994-07-19 Schaltung zur reduzierung von gleichzeitigem transientem leiten

Country Status (6)

Country Link
US (1) US5418474A (de)
EP (1) EP0720791B1 (de)
JP (1) JP3437578B2 (de)
KR (1) KR960705407A (de)
DE (1) DE69420573T2 (de)
WO (1) WO1995008871A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3224712B2 (ja) * 1995-06-20 2001-11-05 富士通株式会社 論理＆レベル変換回路及び半導体装置
US5789942A (en) * 1995-09-07 1998-08-04 Nec Corporation High speed signal level converting circuit having a reduced consumed electric power
KR0172373B1 (ko) * 1995-09-14 1999-03-30 김광호 반도체 메모리 장치의 데이타 출력버퍼
US5880599A (en) * 1996-12-11 1999-03-09 Lsi Logic Corporation On/off control for a balanced differential current mode driver
US6066963A (en) 1997-09-29 2000-05-23 Cypress Semiconductor Corp MOS output driver, and circuit and method of controlling same
US8324934B1 (en) * 2011-01-17 2012-12-04 Lattice Semiconductor Corporation Programmable buffer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818401A (en) * 1988-07-18 1989-04-04 Lawrence William J Rotary filtration device
US5036222A (en) * 1990-02-22 1991-07-30 National Semiconductor Corporation Output buffer circuit with output voltage sensing for reducing switching induced noise
JP2930440B2 (ja) * 1991-04-15 1999-08-03 沖電気工業株式会社 半導体集積回路
KR930008656B1 (ko) * 1991-07-19 1993-09-11 삼성전자 주식회사 노이즈가 억제되는 데이타 출력 버퍼
US5136190A (en) * 1991-08-07 1992-08-04 Micron Technology, Inc. CMOS voltage level translator circuit
US5220209A (en) * 1991-09-27 1993-06-15 National Semiconductor Corporation Edge rate controlled output buffer circuit with controlled charge storage
US5280203A (en) * 1992-05-15 1994-01-18 Altera Corporation Look-ahead asynchronous register set/reset in programmable logic device
US5300832A (en) * 1992-11-10 1994-04-05 Sun Microsystems, Inc. Voltage interfacing buffer with isolation transistors used for overvoltage protection

Also Published As

Publication number Publication date
WO1995008871A1 (en) 1995-03-30
JP3437578B2 (ja) 2003-08-18
DE69420573D1 (de) 1999-10-14
EP0720791A1 (de) 1996-07-10
EP0720791B1 (de) 1999-09-08
KR960705407A (ko) 1996-10-09
US5418474A (en) 1995-05-23
JPH09503107A (ja) 1997-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee