DE69419806D1 - Herstellungsverfahren von Kontakten mit niedrigem Widerstand an den Übergang zwischen Gebieten mit verschiedenen Leitungstypen - Google Patents

Herstellungsverfahren von Kontakten mit niedrigem Widerstand an den Übergang zwischen Gebieten mit verschiedenen Leitungstypen

Info

Publication number
DE69419806D1
DE69419806D1 DE69419806T DE69419806T DE69419806D1 DE 69419806 D1 DE69419806 D1 DE 69419806D1 DE 69419806 T DE69419806 T DE 69419806T DE 69419806 T DE69419806 T DE 69419806T DE 69419806 D1 DE69419806 D1 DE 69419806D1
Authority
DE
Germany
Prior art keywords
conductors
transition
areas
manufacturing
different types
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69419806T
Other languages
English (en)
Other versions
DE69419806T2 (de
Inventor
Robert Louis Hodges
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69419806D1 publication Critical patent/DE69419806D1/de
Publication of DE69419806T2 publication Critical patent/DE69419806T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
DE69419806T 1993-04-29 1994-04-26 Herstellungsverfahren von Kontakten mit niedrigem Widerstand an den Übergang zwischen Gebieten mit verschiedenen Leitungstypen Expired - Fee Related DE69419806T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/055,077 US5432129A (en) 1993-04-29 1993-04-29 Method of forming low resistance contacts at the junction between regions having different conductivity types

Publications (2)

Publication Number Publication Date
DE69419806D1 true DE69419806D1 (de) 1999-09-09
DE69419806T2 DE69419806T2 (de) 2000-01-13

Family

ID=21995434

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419806T Expired - Fee Related DE69419806T2 (de) 1993-04-29 1994-04-26 Herstellungsverfahren von Kontakten mit niedrigem Widerstand an den Übergang zwischen Gebieten mit verschiedenen Leitungstypen

Country Status (4)

Country Link
US (2) US5432129A (de)
EP (1) EP0622844B1 (de)
JP (1) JP3688734B2 (de)
DE (1) DE69419806T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2978736B2 (ja) * 1994-06-21 1999-11-15 日本電気株式会社 半導体装置の製造方法
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
US5534451A (en) * 1995-04-27 1996-07-09 Taiwan Semiconductor Manufacturing Company Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance
US5734179A (en) * 1995-12-12 1998-03-31 Advanced Micro Devices, Inc. SRAM cell having single layer polysilicon thin film transistors
KR100189997B1 (ko) * 1995-12-27 1999-06-01 윤종용 불휘발성 메모리 장치
US5869391A (en) * 1996-08-20 1999-02-09 Micron Technology, Inc. Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry
JPH10150198A (ja) * 1996-11-18 1998-06-02 Mitsubishi Electric Corp 薄膜トランジスタおよびその製造方法
EP0847081A1 (de) * 1996-12-09 1998-06-10 Texas Instruments Incorporated Verbesserungen in, an oder in Bezug auf Halbleitervorrichtungen
US6121663A (en) 1997-05-22 2000-09-19 Advanced Micro Devices, Inc. Local interconnects for improved alignment tolerance and size reduction
US5895264A (en) * 1997-07-30 1999-04-20 Chartered Semiconductor Manufacturing Ltd. Method for forming stacked polysilicon
US6444553B1 (en) * 1997-09-15 2002-09-03 University Of Houston Junction formation with diffusion barrier for silicide contacts and method for forming
US6143617A (en) * 1998-02-23 2000-11-07 Taiwan Semiconductor Manufacturing Company Composite capacitor electrode for a DRAM cell
US6335294B1 (en) * 1999-04-22 2002-01-01 International Business Machines Corporation Wet cleans for cobalt disilicide processing
US6180462B1 (en) * 1999-06-07 2001-01-30 United Microelectronics Corp. Method of fabricating an analog integrated circuit with ESD protection
US6794295B1 (en) 2000-05-26 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method to improve stability and reliability of CVD low K dielectric
US6365446B1 (en) 2000-07-03 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process
US6593234B2 (en) * 2001-07-24 2003-07-15 Micron Technology, Inc. Methods of utilizing metal rich silicide in forming semiconductor constructions
US20040166687A1 (en) * 2003-02-26 2004-08-26 Yung-Chang Lin Method for forming a polycide gate and structure of the same
KR100615085B1 (ko) 2004-01-12 2006-08-22 삼성전자주식회사 노드 콘택 구조체들, 이를 채택하는 반도체소자들, 이를채택하는 에스램 셀들 및 이를 제조하는 방법들
US7829400B2 (en) * 2005-01-12 2010-11-09 Sharp Kabushiki Kaisha Semiconductor device fabrication method and semiconductor device
KR100815956B1 (ko) * 2006-09-05 2008-03-21 동부일렉트로닉스 주식회사 반도체 소자의 게이트 콘택 제조 방법
US10763207B2 (en) 2017-11-21 2020-09-01 Samsung Electronics Co., Ltd. Interconnects having long grains and methods of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
JPS6191974A (ja) * 1984-10-11 1986-05-10 Kanegafuchi Chem Ind Co Ltd 耐熱性マルチジヤンクシヨン型半導体素子
US5059554A (en) * 1989-06-23 1991-10-22 Sgs-Thomson Microelectronics, Inc. Method for forming polycrystalline silicon contacts
KR920004368B1 (ko) * 1989-09-04 1992-06-04 재단법인 한국전자통신연구소 분리병합형 홈의 구조를 갖는 d램셀과 그 제조방법
US5151387A (en) * 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
JPH0541378A (ja) * 1991-03-15 1993-02-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3074758B2 (ja) * 1991-03-28 2000-08-07 日本電気株式会社 スタティック半導体記憶装置及びその製造方法
US5187114A (en) * 1991-06-03 1993-02-16 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline P-channel load devices

Also Published As

Publication number Publication date
US5432129A (en) 1995-07-11
EP0622844B1 (de) 1999-08-04
US5541455A (en) 1996-07-30
EP0622844A1 (de) 1994-11-02
DE69419806T2 (de) 2000-01-13
JP3688734B2 (ja) 2005-08-31
JPH0750276A (ja) 1995-02-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee