DE69419186T2 - Verfahren zur Ätzung eines halbleitenden Substrats - Google Patents

Verfahren zur Ätzung eines halbleitenden Substrats

Info

Publication number
DE69419186T2
DE69419186T2 DE69419186T DE69419186T DE69419186T2 DE 69419186 T2 DE69419186 T2 DE 69419186T2 DE 69419186 T DE69419186 T DE 69419186T DE 69419186 T DE69419186 T DE 69419186T DE 69419186 T2 DE69419186 T2 DE 69419186T2
Authority
DE
Germany
Prior art keywords
etching
etching mask
semiconductor substrate
film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69419186T
Other languages
German (de)
English (en)
Other versions
DE69419186D1 (de
Inventor
Hideo Nagai
Hideyuki Nakanishi
Akira Ueno
Akio Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE69419186D1 publication Critical patent/DE69419186D1/de
Publication of DE69419186T2 publication Critical patent/DE69419186T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Micromachines (AREA)
DE69419186T 1993-01-07 1994-01-05 Verfahren zur Ätzung eines halbleitenden Substrats Expired - Lifetime DE69419186T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00116193A JP3205103B2 (ja) 1993-01-07 1993-01-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69419186D1 DE69419186D1 (de) 1999-07-29
DE69419186T2 true DE69419186T2 (de) 1999-10-21

Family

ID=11493716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419186T Expired - Lifetime DE69419186T2 (de) 1993-01-07 1994-01-05 Verfahren zur Ätzung eines halbleitenden Substrats

Country Status (4)

Country Link
US (1) US5478438A (ja)
EP (1) EP0607808B1 (ja)
JP (1) JP3205103B2 (ja)
DE (1) DE69419186T2 (ja)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651855A (en) * 1992-07-28 1997-07-29 Micron Technology, Inc. Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
US6248429B1 (en) 1998-07-06 2001-06-19 Micron Technology, Inc. Metallized recess in a substrate
US6479395B1 (en) * 1999-11-02 2002-11-12 Alien Technology Corporation Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
US6623579B1 (en) 1999-11-02 2003-09-23 Alien Technology Corporation Methods and apparatus for fluidic self assembly
US6810057B1 (en) 1999-11-25 2004-10-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and optical pickup device
US6885786B2 (en) * 2001-02-07 2005-04-26 Shipley Company, L.L.C. Combined wet and dry etching process for micromachining of crystalline materials
US6907150B2 (en) * 2001-02-07 2005-06-14 Shipley Company, L.L.C. Etching process for micromachining crystalline materials and devices fabricated thereby
US20030021572A1 (en) * 2001-02-07 2003-01-30 Steinberg Dan A. V-groove with tapered depth and method for making
US6964804B2 (en) * 2001-02-14 2005-11-15 Shipley Company, L.L.C. Micromachined structures made by combined wet and dry etching
US20020195417A1 (en) * 2001-04-20 2002-12-26 Steinberg Dan A. Wet and dry etching process on <110> silicon and resulting structures
CN1545732A (zh) * 2001-07-19 2004-11-10 希普雷公司 用于显微机械加工晶体材料的蚀刻工艺和由此制造的装置
GB0128617D0 (en) * 2001-11-29 2002-01-23 Denselight Semiconductors Pte Self-aligned v-groove and deep trench etching of semiconductors
DE10203998A1 (de) * 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
JP4732711B2 (ja) 2003-05-23 2011-07-27 アイピー・キューブ・パートナーズ・カンパニー・リミテッド 結晶性材料をマイクロマシニングするためのエッチング方法、およびこれによって製造されたデバイス
JP5226488B2 (ja) 2008-12-05 2013-07-03 浜松ホトニクス株式会社 光素子モジュールの製造方法
CN104425240B (zh) * 2013-09-05 2018-05-08 北京北方华创微电子装备有限公司 基片刻蚀方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100733A (en) * 1980-12-15 1982-06-23 Fujitsu Ltd Etching method for semiconductor substrate
US4863560A (en) * 1988-08-22 1989-09-05 Xerox Corp Fabrication of silicon structures by single side, multiple step etching process
DE58909602D1 (de) * 1989-09-22 1996-03-21 Siemens Ag Verfahren zum anisotropen Ätzen von Silizium
CH682528A5 (fr) * 1990-03-16 1993-09-30 Westonbridge Int Ltd Procédé de réalisation par attaque chimique d'au moins une cavité dans un substrat et substrat obtenu par ce procédé.
US5277755A (en) * 1991-12-09 1994-01-11 Xerox Corporation Fabrication of three dimensional silicon devices by single side, two-step etching process

Also Published As

Publication number Publication date
JPH06204208A (ja) 1994-07-22
EP0607808A3 (en) 1997-04-09
US5478438A (en) 1995-12-26
EP0607808B1 (en) 1999-06-23
DE69419186D1 (de) 1999-07-29
JP3205103B2 (ja) 2001-09-04
EP0607808A2 (en) 1994-07-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP