DE69418445D1 - MOS-Bauelement mit einer drainseitigen Kanalimplantation - Google Patents

MOS-Bauelement mit einer drainseitigen Kanalimplantation

Info

Publication number
DE69418445D1
DE69418445D1 DE69418445T DE69418445T DE69418445D1 DE 69418445 D1 DE69418445 D1 DE 69418445D1 DE 69418445 T DE69418445 T DE 69418445T DE 69418445 T DE69418445 T DE 69418445T DE 69418445 D1 DE69418445 D1 DE 69418445D1
Authority
DE
Germany
Prior art keywords
drainage
side channel
mos device
channel implantation
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69418445T
Other languages
English (en)
Other versions
DE69418445T2 (de
Inventor
Robert B Richart
Shyam G Garg
Bradley T Moore Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69418445D1 publication Critical patent/DE69418445D1/de
Application granted granted Critical
Publication of DE69418445T2 publication Critical patent/DE69418445T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69418445T 1993-12-10 1994-12-12 MOS-Bauelement mit einer drainseitigen Kanalimplantation Expired - Lifetime DE69418445T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/165,112 US5427963A (en) 1993-12-10 1993-12-10 Method of making a MOS device with drain side channel implant

Publications (2)

Publication Number Publication Date
DE69418445D1 true DE69418445D1 (de) 1999-06-17
DE69418445T2 DE69418445T2 (de) 2000-01-20

Family

ID=22597473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69418445T Expired - Lifetime DE69418445T2 (de) 1993-12-10 1994-12-12 MOS-Bauelement mit einer drainseitigen Kanalimplantation

Country Status (5)

Country Link
US (1) US5427963A (de)
EP (1) EP0662707B1 (de)
JP (1) JP4456673B2 (de)
DE (1) DE69418445T2 (de)
ES (1) ES2131171T3 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5756385A (en) * 1994-03-30 1998-05-26 Sandisk Corporation Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US5661053A (en) * 1994-05-25 1997-08-26 Sandisk Corporation Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US5744372A (en) * 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
EP0793238A1 (de) * 1996-02-29 1997-09-03 STMicroelectronics S.r.l. Elektrisch programmierbare nichtflüchtige Speicherzelle für eine verringerte Anzahl von Programmierzyklen
US5830794A (en) * 1996-03-11 1998-11-03 Ricoh Company, Ltd. Method of fabricating semiconductor memory
US5770880A (en) * 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US5963809A (en) * 1997-06-26 1999-10-05 Advanced Micro Devices, Inc. Asymmetrical MOSFET with gate pattern after source/drain formation
US6124212A (en) * 1997-10-08 2000-09-26 Taiwan Semiconductor Manufacturing Co. High density plasma (HDP) etch method for suppressing micro-loading effects when etching polysilicon layers
US6372590B1 (en) 1997-10-15 2002-04-16 Advanced Micro Devices, Inc. Method for making transistor having reduced series resistance
US6127222A (en) * 1997-12-16 2000-10-03 Advanced Micro Devices, Inc. Non-self-aligned side channel implants for flash memory cells
US6103602A (en) * 1997-12-17 2000-08-15 Advanced Micro Devices, Inc. Method and system for providing a drain side pocket implant
US6303454B1 (en) 1998-02-02 2001-10-16 Taiwan Semiconductor Manufacturing Company Process for a snap-back flash EEPROM cell
JP4236722B2 (ja) * 1998-02-05 2009-03-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6225659B1 (en) * 1998-03-30 2001-05-01 Advanced Micro Devices, Inc. Trenched gate semiconductor device and method for low power applications
KR100524460B1 (ko) * 1998-12-30 2006-01-12 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법_
US6177316B1 (en) * 1999-10-05 2001-01-23 Advanced Micro Devices, Inc. Post barrier metal contact implantation to minimize out diffusion for NAND device
KR100302190B1 (ko) * 1999-10-07 2001-11-02 윤종용 이이피롬 소자 및 그 제조방법
US6875624B2 (en) * 2002-05-08 2005-04-05 Taiwan Semiconductor Manufacturing Co. Ltd. Combined E-beam and optical exposure semiconductor lithography
US7727838B2 (en) * 2007-07-27 2010-06-01 Texas Instruments Incorporated Method to improve transistor Tox using high-angle implants with no additional masks
US20110058410A1 (en) * 2009-09-08 2011-03-10 Hitachi, Ltd. Semiconductor memory device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182171A (ja) * 1984-02-29 1985-09-17 Oki Electric Ind Co Ltd 半導体装置の製造方法
US5304505A (en) * 1989-03-22 1994-04-19 Emanuel Hazani Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
JP2600301B2 (ja) * 1988-06-28 1997-04-16 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2547622B2 (ja) * 1988-08-26 1996-10-23 三菱電機株式会社 不揮発性半導体記憶装置
US4999812A (en) * 1988-11-23 1991-03-12 National Semiconductor Corp. Architecture for a flash erase EEPROM memory
US5070032A (en) * 1989-03-15 1991-12-03 Sundisk Corporation Method of making dense flash eeprom semiconductor memory structures
US5536957A (en) * 1990-01-16 1996-07-16 Mitsubishi Denki Kabushiki Kaisha MOS field effect transistor having source/drain regions surrounded by impurity wells
JP2817393B2 (ja) * 1990-11-14 1998-10-30 日本電気株式会社 半導体記憶装置の製造方法
US5120671A (en) * 1990-11-29 1992-06-09 Intel Corporation Process for self aligning a source region with a field oxide region and a polysilicon gate
DE69224453T2 (de) * 1991-10-01 1998-09-24 Nippon Electric Co Verfahren zur Herstellung von einem LDD-MOSFET

Also Published As

Publication number Publication date
US5427963A (en) 1995-06-27
EP0662707B1 (de) 1999-05-12
JPH07202049A (ja) 1995-08-04
JP4456673B2 (ja) 2010-04-28
DE69418445T2 (de) 2000-01-20
EP0662707A1 (de) 1995-07-12
ES2131171T3 (es) 1999-07-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GARAND CAYMAN, KY