DE69408671T2 - Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer - Google Patents

Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer

Info

Publication number
DE69408671T2
DE69408671T2 DE69408671T DE69408671T DE69408671T2 DE 69408671 T2 DE69408671 T2 DE 69408671T2 DE 69408671 T DE69408671 T DE 69408671T DE 69408671 T DE69408671 T DE 69408671T DE 69408671 T2 DE69408671 T2 DE 69408671T2
Authority
DE
Germany
Prior art keywords
production
silicon wafer
oxide layers
buried oxide
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69408671T
Other languages
English (en)
Other versions
DE69408671D1 (de
Inventor
Salvatore Ugo Campisano
Vito Raineri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Publication of DE69408671D1 publication Critical patent/DE69408671D1/de
Application granted granted Critical
Publication of DE69408671T2 publication Critical patent/DE69408671T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
DE69408671T 1994-09-23 1994-09-23 Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer Expired - Fee Related DE69408671T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830452A EP0703608B1 (de) 1994-09-23 1994-09-23 Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer

Publications (2)

Publication Number Publication Date
DE69408671D1 DE69408671D1 (de) 1998-04-02
DE69408671T2 true DE69408671T2 (de) 1998-06-18

Family

ID=8218534

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408671T Expired - Fee Related DE69408671T2 (de) 1994-09-23 1994-09-23 Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer

Country Status (4)

Country Link
US (1) US5723372A (de)
EP (1) EP0703608B1 (de)
JP (1) JP2777783B2 (de)
DE (1) DE69408671T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69430913D1 (de) * 1994-07-25 2002-08-08 Cons Ric Microelettronica Verfahren zur lokalen Reduzierung der Ladungsträgerlebensdauer
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
DE19750167B4 (de) * 1997-11-12 2006-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung integrierter Schaltkreise
US20080203484A1 (en) * 2007-02-23 2008-08-28 Infineon Technologies Ag Field effect transistor arrangement and method of producing a field effect transistor arrangement
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2563377B1 (fr) * 1984-04-19 1987-01-23 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
JPS61180447A (ja) * 1985-02-05 1986-08-13 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
GB8725497D0 (en) * 1987-10-30 1987-12-02 Atomic Energy Authority Uk Isolation of silicon
US5043292A (en) * 1990-05-31 1991-08-27 National Semiconductor Corporation Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5372952A (en) * 1992-04-03 1994-12-13 National Semiconductor Corporation Method for forming isolated semiconductor structures

Also Published As

Publication number Publication date
JP2777783B2 (ja) 1998-07-23
JPH08111453A (ja) 1996-04-30
EP0703608A1 (de) 1996-03-27
EP0703608B1 (de) 1998-02-25
DE69408671D1 (de) 1998-04-02
US5723372A (en) 1998-03-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee