DE69328070T2 - Maske zum Auswählen von Kompenenten in einem Verbundoperand - Google Patents
Maske zum Auswählen von Kompenenten in einem VerbundoperandInfo
- Publication number
- DE69328070T2 DE69328070T2 DE69328070T DE69328070T DE69328070T2 DE 69328070 T2 DE69328070 T2 DE 69328070T2 DE 69328070 T DE69328070 T DE 69328070T DE 69328070 T DE69328070 T DE 69328070T DE 69328070 T2 DE69328070 T2 DE 69328070T2
- Authority
- DE
- Germany
- Prior art keywords
- mask
- selecting components
- operand
- compound
- compound operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 150000001875 compounds Chemical class 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/764—Masking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/993,938 US5651121A (en) | 1992-12-18 | 1992-12-18 | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69328070D1 DE69328070D1 (de) | 2000-04-20 |
DE69328070T2 true DE69328070T2 (de) | 2000-07-13 |
Family
ID=25540099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69328070T Expired - Lifetime DE69328070T2 (de) | 1992-12-18 | 1993-12-08 | Maske zum Auswählen von Kompenenten in einem Verbundoperand |
Country Status (4)
Country | Link |
---|---|
US (1) | US5651121A (de) |
EP (1) | EP0602886B1 (de) |
JP (1) | JP3584053B2 (de) |
DE (1) | DE69328070T2 (de) |
Families Citing this family (42)
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US6385634B1 (en) | 1995-08-31 | 2002-05-07 | Intel Corporation | Method for performing multiply-add operations on packed data |
US7395298B2 (en) * | 1995-08-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |
JPH0969047A (ja) | 1995-09-01 | 1997-03-11 | Sony Corp | Risc型マイクロプロセッサおよび情報処理装置 |
JP3433588B2 (ja) * | 1995-10-19 | 2003-08-04 | 株式会社デンソー | マスクデータ生成回路及びビットフィールド操作回路 |
US6036350A (en) * | 1995-12-20 | 2000-03-14 | Intel Corporation | Method of sorting signed numbers and solving absolute differences using packed instructions |
US5907842A (en) * | 1995-12-20 | 1999-05-25 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |
US5983291A (en) * | 1996-09-24 | 1999-11-09 | Cirrus Logic, Inc. | System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently |
US5832288A (en) * | 1996-10-18 | 1998-11-03 | Samsung Electronics Co., Ltd. | Element-select mechanism for a vector processor |
US5946222A (en) * | 1996-12-20 | 1999-08-31 | Oak Technology, Inc. | Method and apparatus for performing a masked byte addition operation |
US20020132252A1 (en) * | 1997-06-16 | 2002-09-19 | Genentech, Inc. | Secreted and transmembrane polypeptides and nucleic acids encoding the same |
US6117508A (en) | 1997-06-27 | 2000-09-12 | Dyneon Llc | Composite articles including a fluoropolymer blend |
US6081824A (en) * | 1998-03-05 | 2000-06-27 | Intel Corporation | Method and apparatus for fast unsigned integral division |
JP4131349B2 (ja) * | 1998-12-09 | 2008-08-13 | ソニー株式会社 | データ変換装置およびデータ変換方法、記録媒体、並びにデータ変換システム |
US6470440B1 (en) * | 1999-05-20 | 2002-10-22 | International Business Machines Corporation | Vector compare and maximum/minimum generation apparatus and method therefor |
US7120781B1 (en) * | 2000-06-30 | 2006-10-10 | Intel Corporation | General purpose register file architecture for aligned simd |
AU2002212570A1 (en) * | 2000-10-24 | 2002-05-15 | Hmi Co., Ltd. | Random number generator |
US6944753B2 (en) * | 2001-04-11 | 2005-09-13 | International Business Machines Corporation | Fixed point unit pipeline allowing partial instruction execution during the instruction dispatch cycle |
US6952711B2 (en) | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US7020788B2 (en) | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US20020184566A1 (en) | 2001-06-01 | 2002-12-05 | Michael Catherwood | Register pointer trap |
US7467178B2 (en) | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US6975679B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US7003543B2 (en) * | 2001-06-01 | 2006-02-21 | Microchip Technology Incorporated | Sticky z bit |
US6934728B2 (en) | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US6937084B2 (en) | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US6985986B2 (en) * | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US6976158B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US7007172B2 (en) | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US7430578B2 (en) * | 2001-10-29 | 2008-09-30 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed byte data |
US7430574B2 (en) * | 2004-06-24 | 2008-09-30 | Intel Corporation | Efficient execution and emulation of bit scan operations |
US7610472B2 (en) * | 2005-06-05 | 2009-10-27 | Apple Inc. | Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option |
WO2007083199A1 (en) * | 2006-01-18 | 2007-07-26 | Freescale Semiconductor, Inc. | Device and method for finding extreme values in a data block |
US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
US9003170B2 (en) * | 2009-12-22 | 2015-04-07 | Intel Corporation | Bit range isolation instructions, methods, and apparatus |
US9323531B2 (en) * | 2013-03-15 | 2016-04-26 | Intel Corporation | Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register |
US9880839B2 (en) * | 2014-04-24 | 2018-01-30 | Intel Corporation | Instruction that performs a scatter write |
US9262704B1 (en) * | 2015-03-04 | 2016-02-16 | Xerox Corporation | Rendering images to lower bits per pixel formats using reduced numbers of registers |
US10423411B2 (en) * | 2015-09-26 | 2019-09-24 | Intel Corporation | Data element comparison processors, methods, systems, and instructions |
US11500680B2 (en) * | 2020-04-24 | 2022-11-15 | Alibaba Group Holding Limited | Systolic array-friendly data placement and control based on masked write |
US11410580B2 (en) * | 2020-08-20 | 2022-08-09 | Facebook Technologies, Llc. | Display non-uniformity correction |
CN112799637B (zh) * | 2021-01-22 | 2023-03-14 | 西安电子科技大学 | 一种并行环境下高吞吐量的模逆计算方法及系统 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4139899A (en) * | 1976-10-18 | 1979-02-13 | Burroughs Corporation | Shift network having a mask generator and a rotator |
US4180861A (en) * | 1978-03-31 | 1979-12-25 | Ncr Corporation | Selectively operable mask generator |
DE3040931C1 (de) * | 1980-10-30 | 1982-04-29 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und Anordnung zur Verknuepfung von Operanden variabler Laenge in Datenverarbeitungsanlagen |
US4592005A (en) * | 1982-07-06 | 1986-05-27 | Sperry Corporation | Masked arithmetic logic unit |
US4785393A (en) * | 1984-07-09 | 1988-11-15 | Advanced Micro Devices, Inc. | 32-Bit extended function arithmetic-logic unit on a single chip |
US5034900A (en) * | 1984-10-05 | 1991-07-23 | Hitachi, Ltd. | Method and apparatus for bit operational process |
JPS6266377A (ja) * | 1985-09-19 | 1987-03-25 | Fujitsu Ltd | マスクパタ−ン生成方式 |
US5056041A (en) * | 1986-12-31 | 1991-10-08 | Texas Instruments Incorporated | Data processing apparatus with improved bit masking capability |
US4775952A (en) * | 1986-05-29 | 1988-10-04 | General Electric Company | Parallel processing system apparatus |
US5060280A (en) * | 1986-09-30 | 1991-10-22 | Canon Kabushiki Kaisha | Masking control for image processing systems |
US4864529A (en) * | 1986-10-09 | 1989-09-05 | North American Philips Corporation | Fast multiplier architecture |
US5129092A (en) * | 1987-06-01 | 1992-07-07 | Applied Intelligent Systems,Inc. | Linear chain of parallel processors and method of using same |
JP2613223B2 (ja) * | 1987-09-10 | 1997-05-21 | 株式会社日立製作所 | 演算装置 |
US5129066A (en) * | 1987-09-17 | 1992-07-07 | International Business Machines Corporation | Bit mask generator circuit using multiple logic units for generating a bit mask sequence |
US4953119A (en) * | 1989-01-27 | 1990-08-28 | Hughes Aircraft Company | Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers |
US5131049A (en) * | 1989-12-08 | 1992-07-14 | Xerox Corporation | Identification, characterization, and segmentation of halftone or stippled regions of binary images by growing a seed to a clipping mask |
US5065437A (en) * | 1989-12-08 | 1991-11-12 | Xerox Corporation | Identification and segmentation of finely textured and solid regions of binary images |
US5048109A (en) * | 1989-12-08 | 1991-09-10 | Xerox Corporation | Detection of highlighted regions |
US5267051A (en) * | 1989-12-22 | 1993-11-30 | Eastman Kodak Company | High speed compression of imagery data |
US5214763A (en) * | 1990-05-10 | 1993-05-25 | International Business Machines Corporation | Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism |
US5280547A (en) * | 1990-06-08 | 1994-01-18 | Xerox Corporation | Dense aggregative hierarhical techniques for data analysis |
JPH0454679A (ja) * | 1990-06-25 | 1992-02-21 | Nec Corp | 演算装置 |
JP2601960B2 (ja) * | 1990-11-15 | 1997-04-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | データ処理方法及びその装置 |
US5315699A (en) * | 1991-03-20 | 1994-05-24 | Research Development Corporation Of Japan | Filtering operation method for very high-speed image processing system |
JP3366633B2 (ja) * | 1991-11-27 | 2003-01-14 | セイコーエプソン株式会社 | ピクセル変更システム及びピクセル変更方法 |
US5450604A (en) * | 1992-12-18 | 1995-09-12 | Xerox Corporation | Data rotation using parallel to serial units that receive data from memory units and rotation buffer that provides rotated data to memory units |
US5375080A (en) * | 1992-12-18 | 1994-12-20 | Xerox Corporation | Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component |
US5437045A (en) * | 1992-12-18 | 1995-07-25 | Xerox Corporation | Parallel processing with subsampling/spreading circuitry and data transfer circuitry to and from any processing unit |
US5408670A (en) * | 1992-12-18 | 1995-04-18 | Xerox Corporation | Performing arithmetic in parallel on composite operands with packed multi-bit components |
US5428804A (en) * | 1992-12-18 | 1995-06-27 | Xerox Corporation | Edge crossing circuitry for SIMD architecture |
US5450603A (en) * | 1992-12-18 | 1995-09-12 | Xerox Corporation | SIMD architecture with transfer register or value source circuitry connected to bus |
-
1992
- 1992-12-18 US US07/993,938 patent/US5651121A/en not_active Expired - Lifetime
-
1993
- 1993-12-08 EP EP93309860A patent/EP0602886B1/de not_active Expired - Lifetime
- 1993-12-08 DE DE69328070T patent/DE69328070T2/de not_active Expired - Lifetime
- 1993-12-17 JP JP31778593A patent/JP3584053B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5651121A (en) | 1997-07-22 |
DE69328070D1 (de) | 2000-04-20 |
EP0602886B1 (de) | 2000-03-15 |
JPH06222918A (ja) | 1994-08-12 |
EP0602886A2 (de) | 1994-06-22 |
EP0602886A3 (en) | 1994-09-07 |
JP3584053B2 (ja) | 2004-11-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |