DE69324534T2 - Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks - Google Patents

Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks

Info

Publication number
DE69324534T2
DE69324534T2 DE69324534T DE69324534T DE69324534T2 DE 69324534 T2 DE69324534 T2 DE 69324534T2 DE 69324534 T DE69324534 T DE 69324534T DE 69324534 T DE69324534 T DE 69324534T DE 69324534 T2 DE69324534 T2 DE 69324534T2
Authority
DE
Germany
Prior art keywords
calculating
power consumption
mos transistors
function block
logic function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69324534T
Other languages
English (en)
Other versions
DE69324534D1 (de
Inventor
Naoko Omori
Michio C O Mitsubishi D Komoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69324534D1 publication Critical patent/DE69324534D1/de
Application granted granted Critical
Publication of DE69324534T2 publication Critical patent/DE69324534T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69324534T 1992-08-05 1993-07-30 Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks Expired - Fee Related DE69324534T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4208891A JPH0660139A (ja) 1992-08-05 1992-08-05 Ｍｏｓトランジスタの論理機能ブロックの消費電力計算装置

Publications (2)

Publication Number Publication Date
DE69324534D1 DE69324534D1 (de) 1999-05-27
DE69324534T2 true DE69324534T2 (de) 1999-10-21

Family

ID=16563842

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69324534T Expired - Fee Related DE69324534T2 (de) 1992-08-05 1993-07-30 Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks

Country Status (4)

Country Link
US (1) US5473548A (de)
EP (1) EP0582918B1 (de)
JP (1) JPH0660139A (de)
DE (1) DE69324534T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602753A (en) * 1994-04-19 1997-02-11 Matsushita Electric Industrial Co., Ltd. Method and apparatus for estimating power dissipation and method and apparatus of determining layout/routing
JPH0844788A (ja) * 1994-05-24 1996-02-16 Toshiba Corp 集積回路の消費電力算出方法及びその装置
US5668732A (en) * 1994-06-03 1997-09-16 Synopsys, Inc. Method for estimating power consumption of a cyclic sequential electronic circuit
US5625803A (en) * 1994-12-14 1997-04-29 Vlsi Technology, Inc. Slew rate based power usage simulation and method
US5712790A (en) * 1995-04-11 1998-01-27 International Business Machines Corporation Method of power reduction in pla's
US5872952A (en) 1995-04-17 1999-02-16 Synopsys, Inc. Integrated circuit power net analysis through simulation
US5805459A (en) * 1995-04-24 1998-09-08 Texas Instruments Incorporated Method of measuring activity in a digital circuit
JPH0927741A (ja) * 1995-07-11 1997-01-28 Mitsubishi Electric Corp 論理回路チェック装置および方法
JP3671504B2 (ja) * 1996-03-05 2005-07-13 ヤマハ株式会社 半導体集積回路のレイアウト設計方法
US5838947A (en) * 1996-04-02 1998-11-17 Synopsys, Inc. Modeling, characterization and simulation of integrated circuit power behavior
US5691910A (en) * 1996-06-10 1997-11-25 Lsi Logic Corporation Generic gate level model for characterization of glitch power in logic cells
US5768145A (en) * 1996-06-11 1998-06-16 Lsi Logic Corporation Parametrized waveform processor for gate-level power analysis tool
US5835380A (en) * 1996-06-11 1998-11-10 Lsi Logic Corporation Simulation based extractor of expected waveforms for gate-level power analysis tool
JP3693420B2 (ja) * 1996-06-20 2005-09-07 株式会社リコー 集積回路の消費電力見積り装置
US5949689A (en) * 1996-10-29 1999-09-07 Synopsys, Inc. Path dependent power modeling
US6212665B1 (en) 1998-03-27 2001-04-03 Synopsys, Inc. Efficient power analysis method for logic cells with many output switchings
US6338025B1 (en) 1998-10-08 2002-01-08 International Business Machines Corp. Data processing system and method to estimate power in mixed dynamic/static CMOS designs
US20020042704A1 (en) * 2000-08-31 2002-04-11 Najm Farid N. Apparatus and methods for characterizing electronic circuits having multiple power supplies
US6721927B2 (en) * 2002-03-29 2004-04-13 International Business Machines Corporation Substituting high performance and low power macros in integrated circuit chips
US7313510B2 (en) * 2003-06-02 2007-12-25 V-Cube Technology Corp. Methods for estimating power requirements of circuit designs
US7032206B2 (en) 2003-08-25 2006-04-18 Hewlett-Packard Development Company, L.P. System and method for iteratively traversing a hierarchical circuit design
US7076752B2 (en) * 2003-08-25 2006-07-11 Hewlett-Packard Development Company, L.P. System and method for determining unmatched design elements in a computer-automated design
JP2008299464A (ja) * 2007-05-30 2008-12-11 Nec Electronics Corp 消費電力計算方法、消費電力計算プログラムおよび消費電力計算装置
US8825464B2 (en) * 2008-09-02 2014-09-02 Oracle America, Inc. Method and apparatus for parallelization of sequential power simulation
JP5821240B2 (ja) * 2011-03-31 2015-11-24 富士通株式会社 プログラム、ライブラリ作成装置、及び方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698760A (en) * 1985-06-06 1987-10-06 International Business Machines Method of optimizing signal timing delays and power consumption in LSI circuits
JPS62189739A (ja) * 1986-02-17 1987-08-19 Hitachi Ltd 半導体集積回路装置
JP2803119B2 (ja) * 1988-12-23 1998-09-24 日本電気株式会社 Ｃｍｏｓゲートアレイ消費電力計算方式
US5282148A (en) * 1989-05-23 1994-01-25 Vlsi Technology, Inc. Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic
US5077676A (en) * 1990-03-30 1991-12-31 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
WO1992011657A1 (en) * 1990-12-19 1992-07-09 Vlsi Technology Inc. Method for predicting capacitance of connection nets on an integrated circuit
US5349542A (en) * 1992-04-02 1994-09-20 Vlsi Technology, Inc. Method for sizing widths of power busses in integrated circuits

Also Published As

Publication number Publication date
EP0582918A3 (de) 1994-11-23
EP0582918B1 (de) 1999-04-21
DE69324534D1 (de) 1999-05-27
EP0582918A2 (de) 1994-02-16
JPH0660139A (ja) 1994-03-04
US5473548A (en) 1995-12-05

Similar Documents

Publication Publication Date Title
DE69324534T2 (de) Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks
DE69301561D1 (de) Vorrichtung für Gleichstrom-Leistungsversorgung
FI941560A0 (fi) Perälaatikon putkipatterilaite
DE69101386D1 (de) Strommess-Schaltung in einem MOS-Leistungstransistor.
DE69330475D1 (de) Aus tetra- oder höherfunktionellen Polyoxyalkylenaminen als Kettenverlängerer hergestellte Polyharnstoff-Elastomere
DE69504128T2 (de) Modulationsdotierter Feldeffekttransistor
DE69321171D1 (de) Gate-Treiberschaltung für einen MOS-Leistungstransistor
ES557586A0 (es) Perfeccionamientos en un dispositivo transistor mos
DK29992D0 (da) Udluftningsventil til tage
FR2734403B1 (fr) Isolement plan dans des circuits integres
DE69316961T2 (de) Verstärkerschaltung in MOS Technologie
DE69416734T2 (de) Logikgatter bestehend aus Halbleitertransistoren
DE69330594T2 (de) Integrierte Schaltungsanordnung für Feldeffekttransitoren
DE69416595D1 (de) Schaltung zur Begrenzung der Ausgangsspannung eines Leistungstransistors
DE9320166U1 (de) Schnappverbindung für in Wandöffnungen einsetzbare Kunststoff-Gehäuse
DE9318684U1 (de) Vorrichtung zur Entfaltung des Uterus durch Spülflüssigkeit im Zuge der Hysteroskopie
FI931317A0 (fi) Foerfarande foer automatisk styrning av foerstaerkningen vid superheterodyn mottagning av radioelektriska signaler samt mottagare foer genomfoerande av foerfarandet
SE9300318D0 (sv) Foerfarande vid anordning foer tillsaettning av kemikalier till dricksvatten i vattenverk
SE9203458D0 (sv) Anordning vid stomibandage
SE9303027D0 (sv) Anordning vid träning av hästar
ITUD930011U1 (it) Parcheggi rettangolari e dodecagonali
IT8467907A0 (it) Dispositivo di memorizzazione temporanea di annunci o messaggi fonici codificati in forma numerica
ATA35293A (de) Schottentor zum wahlweisen sperren der wasserführung
SE9400201D0 (sv) Anordning vid utslagsplats
SE9400273D0 (sv) Anordning vid utslagsplats

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee