DE69322244D1 - Verfahren und System zur Erhöhung der Systemspeichergleichzeitigkeit eines Multiprozessor-Rechnersystems - Google Patents
Verfahren und System zur Erhöhung der Systemspeichergleichzeitigkeit eines Multiprozessor-RechnersystemsInfo
- Publication number
- DE69322244D1 DE69322244D1 DE69322244T DE69322244T DE69322244D1 DE 69322244 D1 DE69322244 D1 DE 69322244D1 DE 69322244 T DE69322244 T DE 69322244T DE 69322244 T DE69322244 T DE 69322244T DE 69322244 D1 DE69322244 D1 DE 69322244D1
- Authority
- DE
- Germany
- Prior art keywords
- simultaneity
- increasing
- multiprocessor computer
- memory
- computer system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US229293A | 1993-01-08 | 1993-01-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69322244D1 true DE69322244D1 (de) | 1999-01-07 |
DE69322244T2 DE69322244T2 (de) | 1999-07-01 |
Family
ID=21700105
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69322244T Expired - Fee Related DE69322244T2 (de) | 1993-01-08 | 1993-12-27 | Verfahren und System zur Erhöhung der Systemspeichergleichzeitigkeit eines Multiprozessor-Rechnersystems |
Country Status (5)
Country | Link |
---|---|
US (1) | US5758120A (de) |
EP (1) | EP0605871B1 (de) |
JP (1) | JP2575598B2 (de) |
CA (1) | CA2107056C (de) |
DE (1) | DE69322244T2 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5835964A (en) * | 1996-04-29 | 1998-11-10 | Microsoft Corporation | Virtual memory system with hardware TLB and unmapped software TLB updated from mapped task address maps using unmapped kernel address map |
US6417848B1 (en) * | 1997-08-25 | 2002-07-09 | Ati International Srl | Pixel clustering for improved graphics throughput |
US6438722B1 (en) * | 1999-08-11 | 2002-08-20 | International Business Machines Corporation | Method and system for testing an integrated circuit |
US6393594B1 (en) * | 1999-08-11 | 2002-05-21 | International Business Machines Corporation | Method and system for performing pseudo-random testing of an integrated circuit |
WO2002088789A1 (en) * | 2001-04-30 | 2002-11-07 | Schott Glas | Fiber optic array assembly and method for making the same |
GB0214669D0 (en) * | 2002-06-26 | 2002-08-07 | Ibm | Method for maintaining data access during failure of a controller |
US7080220B2 (en) * | 2003-07-03 | 2006-07-18 | International Business Machines Corporation | Page replacement with a re-reference indicator |
US7739476B2 (en) * | 2005-11-04 | 2010-06-15 | Apple Inc. | R and C bit update handling |
US8397029B2 (en) * | 2007-12-19 | 2013-03-12 | International Business Machines Corporation | System and method for cache coherency in a multiprocessor system |
GB2474250B (en) * | 2009-10-07 | 2015-05-06 | Advanced Risc Mach Ltd | Video reference frame retrieval |
CN103229152B (zh) * | 2010-11-26 | 2016-10-19 | 国际商业机器公司 | 高速缓存一致性控制方法、系统和程序 |
WO2012137599A1 (ja) * | 2011-04-05 | 2012-10-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9330017B2 (en) * | 2012-11-02 | 2016-05-03 | International Business Machines Corporation | Suppressing virtual address translation utilizing bits and instruction tagging |
EP3060992B1 (de) | 2013-10-27 | 2019-11-27 | Advanced Micro Devices, Inc. | Eingabe/ausgabe-speicherkarteneinheit und northbridge-element |
US9785554B2 (en) * | 2014-05-30 | 2017-10-10 | International Business Machines Corporation | Synchronizing updates of page table status indicators in a multiprocessing environment |
US9384133B2 (en) | 2014-05-30 | 2016-07-05 | International Business Machines Corporation | Synchronizing updates of page table status indicators and performing bulk operations |
US10671754B2 (en) | 2017-10-20 | 2020-06-02 | International Business Machines Corporation | Detection of sensitive personal information in a storage device |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3581291A (en) * | 1968-10-31 | 1971-05-25 | Hitachi Ltd | Memory control system in multiprocessing system |
US3735360A (en) * | 1971-08-25 | 1973-05-22 | Ibm | High speed buffer operation in a multi-processing system |
JPS51115737A (en) * | 1975-03-24 | 1976-10-12 | Hitachi Ltd | Adress conversion versus control system |
US4293910A (en) * | 1979-07-02 | 1981-10-06 | International Business Machines Corporation | Reconfigurable key-in-storage means for protecting interleaved main storage |
US4394731A (en) * | 1980-11-10 | 1983-07-19 | International Business Machines Corporation | Cache storage line shareability control for a multiprocessor system |
US4520441A (en) * | 1980-12-15 | 1985-05-28 | Hitachi, Ltd. | Data processing system |
US4463420A (en) * | 1982-02-23 | 1984-07-31 | International Business Machines Corporation | Multiprocessor cache replacement under task control |
US4577274A (en) * | 1983-07-11 | 1986-03-18 | At&T Bell Laboratories | Demand paging scheme for a multi-ATB shared memory processing system |
US4731739A (en) * | 1983-08-29 | 1988-03-15 | Amdahl Corporation | Eviction control apparatus |
JPS60134949A (ja) * | 1983-12-23 | 1985-07-18 | Hitachi Ltd | ストレ−ジキ−制御方式 |
US4669043A (en) * | 1984-02-17 | 1987-05-26 | Signetics Corporation | Memory access controller |
US4731740A (en) * | 1984-06-30 | 1988-03-15 | Kabushiki Kaisha Toshiba | Translation lookaside buffer control system in computer or virtual memory control scheme |
US4792895A (en) * | 1984-07-30 | 1988-12-20 | International Business Machines Corp. | Instruction processing in higher level virtual machines by a real machine |
US4811206A (en) * | 1986-01-16 | 1989-03-07 | Ibm Corporation | Data processing system with overlapped address translation and address computation |
US4885680A (en) * | 1986-07-25 | 1989-12-05 | International Business Machines Corporation | Method and apparatus for efficiently handling temporarily cacheable data |
JPS63157250A (ja) * | 1986-12-22 | 1988-06-30 | Hitachi Ltd | キ−記憶装置 |
JPH0812636B2 (ja) * | 1986-12-24 | 1996-02-07 | 株式会社東芝 | 仮想記憶制御方式の計算機システム |
US5023776A (en) * | 1988-02-22 | 1991-06-11 | International Business Machines Corp. | Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage |
JPH02162439A (ja) * | 1988-12-15 | 1990-06-22 | Fujitsu Ltd | 共有メモリのフリーリスト管理方式 |
US5075848A (en) * | 1989-12-22 | 1991-12-24 | Intel Corporation | Object lifetime control in an object-oriented memory protection mechanism |
US5339397A (en) * | 1990-10-12 | 1994-08-16 | International Business Machines Corporation | Hardware primary directory lock |
US5317705A (en) * | 1990-10-24 | 1994-05-31 | International Business Machines Corporation | Apparatus and method for TLB purge reduction in a multi-level machine system |
JP2581323B2 (ja) * | 1990-12-06 | 1997-02-12 | 富士通株式会社 | 参照ビット,変更ビットの更新方法 |
JPH0736170B2 (ja) * | 1991-04-03 | 1995-04-19 | 工業技術院長 | マルチプロセッサシステム |
-
1993
- 1993-09-27 CA CA002107056A patent/CA2107056C/en not_active Expired - Fee Related
- 1993-12-15 JP JP5315563A patent/JP2575598B2/ja not_active Expired - Lifetime
- 1993-12-27 DE DE69322244T patent/DE69322244T2/de not_active Expired - Fee Related
- 1993-12-27 EP EP93120939A patent/EP0605871B1/de not_active Expired - Lifetime
-
1996
- 1996-08-20 US US08/700,132 patent/US5758120A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0605871B1 (de) | 1998-11-25 |
EP0605871A2 (de) | 1994-07-13 |
EP0605871A3 (de) | 1994-10-19 |
DE69322244T2 (de) | 1999-07-01 |
US5758120A (en) | 1998-05-26 |
CA2107056A1 (en) | 1994-07-09 |
JP2575598B2 (ja) | 1997-01-29 |
CA2107056C (en) | 1998-06-23 |
JPH06236353A (ja) | 1994-08-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |