DE69229716D1 - Schaltungsarchitektur zum mehrkanaligen DMA-Betrieb - Google Patents

Schaltungsarchitektur zum mehrkanaligen DMA-Betrieb

Info

Publication number
DE69229716D1
DE69229716D1 DE69229716T DE69229716T DE69229716D1 DE 69229716 D1 DE69229716 D1 DE 69229716D1 DE 69229716 T DE69229716 T DE 69229716T DE 69229716 T DE69229716 T DE 69229716T DE 69229716 D1 DE69229716 D1 DE 69229716D1
Authority
DE
Germany
Prior art keywords
circuit architecture
dma operation
channel dma
channel
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229716T
Other languages
English (en)
Other versions
DE69229716T2 (de
Inventor
Martin Sodos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69229716D1 publication Critical patent/DE69229716D1/de
Application granted granted Critical
Publication of DE69229716T2 publication Critical patent/DE69229716T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Time-Division Multiplex Systems (AREA)
DE69229716T 1991-12-30 1992-12-07 Schaltungsarchitektur zum mehrkanaligen DMA-Betrieb Expired - Fee Related DE69229716T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/814,765 US5386532A (en) 1991-12-30 1991-12-30 Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels

Publications (2)

Publication Number Publication Date
DE69229716D1 true DE69229716D1 (de) 1999-09-09
DE69229716T2 DE69229716T2 (de) 2000-03-02

Family

ID=25215952

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229716T Expired - Fee Related DE69229716T2 (de) 1991-12-30 1992-12-07 Schaltungsarchitektur zum mehrkanaligen DMA-Betrieb

Country Status (5)

Country Link
US (1) US5386532A (de)
EP (1) EP0550163B1 (de)
JP (1) JP3273202B2 (de)
KR (1) KR0142175B1 (de)
DE (1) DE69229716T2 (de)

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JP3525518B2 (ja) * 1994-10-13 2004-05-10 ヤマハ株式会社 データ転送装置
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
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EP0732659B1 (de) * 1995-03-17 2001-08-08 LSI Logic Corporation (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5870627A (en) * 1995-12-20 1999-02-09 Cirrus Logic, Inc. System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue
US5828901A (en) * 1995-12-21 1998-10-27 Cirrus Logic, Inc. Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer
US5758187A (en) * 1996-03-15 1998-05-26 Adaptec, Inc. Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure
US5797034A (en) * 1996-03-15 1998-08-18 Adaptec, Inc. Method for specifying execution of only one of a pair of I/O command blocks in a chain structure
US5768621A (en) * 1996-03-15 1998-06-16 Adaptec, Inc. Chain manager for use in executing a chain of I/O command blocks
US5812877A (en) * 1996-03-15 1998-09-22 Adaptec, Inc. I/O command block chain structure in a memory
US5884050A (en) * 1996-06-21 1999-03-16 Digital Equipment Corporation Mechanism for high bandwidth DMA transfers in a PCI environment
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
JPH10228442A (ja) * 1997-02-17 1998-08-25 Canon Inc ダイレクト・メモリ・アクセスによるデータ受信装置，方法および記憶媒体
US6199121B1 (en) * 1998-08-07 2001-03-06 Oak Technology, Inc. High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions
DE10050980A1 (de) * 2000-10-13 2002-05-02 Systemonic Ag Speicherkonfiguration mit I/O-Unterstützung
US6839753B2 (en) * 2001-02-23 2005-01-04 Cardiopulmonary Corporation Network monitoring systems for medical devices
US20020133699A1 (en) * 2001-03-13 2002-09-19 Pueschel Roy Myron Method and apparatus to regulate use of freely exchanged files and streams
US7054986B2 (en) * 2001-03-30 2006-05-30 Nokia Corporation Programmable CPU/interface buffer structure using dual port RAM
US20020184381A1 (en) * 2001-05-30 2002-12-05 Celox Networks, Inc. Method and apparatus for dynamically controlling data flow on a bi-directional data bus
US6842791B2 (en) * 2002-03-20 2005-01-11 Intel Corporation Method and apparatus for memory efficient fast VLAN lookups and inserts in hardware-based packet switches
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
DE102004039932A1 (de) * 2004-08-17 2006-03-09 Phoenix Contact Gmbh & Co. Kg Verfahren und Vorrichtung zur Busankopplung sicherheitsrelevanter Prozesse
US7185123B2 (en) * 2004-09-15 2007-02-27 Qualcomm Incorporated Method and apparatus for allocating bandwidth on a transmit channel of a bus
DE602004012106T2 (de) * 2004-10-11 2009-02-19 Texas Instruments Inc., Dallas Multikanal-DMA mit gemeinsamem FIFO-Puffer
US20060253659A1 (en) * 2005-05-05 2006-11-09 International Business Machines Corporation Method and virtual port register array for implementing shared access to a register array port by multiple sources
US8149854B2 (en) * 2005-06-30 2012-04-03 Intel Corporation Multi-threaded transmit transport engine for storage devices
EP1908177B1 (de) * 2005-07-26 2012-03-14 Thomson Licensing Korrelator zur primärzellensuche unter verwendung einer speicherarchitektur
US20090083470A1 (en) * 2007-09-24 2009-03-26 Ali Corporation System on chip device and method for multiple device access through a shared interface
US9438844B2 (en) * 2008-04-08 2016-09-06 Imagine Communications Corp. Video multiviewer system using direct memory access (DMA) registers and block RAM
CN102713912B (zh) * 2009-10-13 2016-06-22 心外部有限公司 用于显示来自医疗设备的数据的方法及装置
KR101685407B1 (ko) 2010-07-29 2016-12-13 삼성전자주식회사 멀티코어 시스템을 위한 다이렉트 메모리 억세스 장치 및 다이렉트 메모리 억세스 장치의 동작 방법
US8447897B2 (en) * 2011-06-24 2013-05-21 Freescale Semiconductor, Inc. Bandwidth control for a direct memory access unit within a data processing system
US9195684B2 (en) 2012-03-02 2015-11-24 Cleversafe, Inc. Redundant task execution in a distributed storage and task network
US9128925B2 (en) 2012-04-24 2015-09-08 Freescale Semiconductor, Inc. System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines
US9380474B2 (en) 2013-03-08 2016-06-28 Cardiopulmonary Corp. Network monitoring for active medical device alarms
CN111831595A (zh) * 2020-06-30 2020-10-27 山东云海国创云计算装备产业创新中心有限公司 一种dma传输方法及相关装置

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US4403282A (en) * 1978-01-23 1983-09-06 Data General Corporation Data processing system using a high speed data channel for providing direct memory access for block data transfers
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
WO1984000222A1 (en) * 1982-06-30 1984-01-19 Elxsi I/o channel bus
US4750150A (en) * 1984-06-25 1988-06-07 Allen-Bradley Company, Inc. I/O scanner for an industrial control
US4750107A (en) * 1985-01-07 1988-06-07 Unisys Corporation Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels
GB2196762B (en) * 1986-10-27 1990-12-19 Burr Brown Ltd Interleaved access to global memory by high priority source
US4831523A (en) * 1986-10-31 1989-05-16 Bull Hn Information Systems Inc. Multiple DMA controller chip sequencer
US4896266A (en) * 1987-06-03 1990-01-23 Bull Hn Information Systems Inc. Bus activity sequence controller
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US5261064A (en) * 1989-10-03 1993-11-09 Advanced Micro Devices, Inc. Burst access memory
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
US5157775A (en) * 1989-12-15 1992-10-20 Eastman Kodak Company Dual port, dual speed image memory access arrangement
US5175825A (en) * 1990-02-02 1992-12-29 Auspex Systems, Inc. High speed, flexible source/destination data burst direct memory access controller
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features

Also Published As

Publication number Publication date
EP0550163B1 (de) 1999-08-04
JPH06266649A (ja) 1994-09-22
EP0550163A1 (de) 1993-07-07
KR0142175B1 (ko) 1998-07-01
DE69229716T2 (de) 2000-03-02
KR930014067A (ko) 1993-07-22
JP3273202B2 (ja) 2002-04-08
US5386532A (en) 1995-01-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee