DE69220152D1 - Prüfmustererzeugungsgerät - Google Patents

Prüfmustererzeugungsgerät

Info

Publication number
DE69220152D1
DE69220152D1 DE69220152T DE69220152T DE69220152D1 DE 69220152 D1 DE69220152 D1 DE 69220152D1 DE 69220152 T DE69220152 T DE 69220152T DE 69220152 T DE69220152 T DE 69220152T DE 69220152 D1 DE69220152 D1 DE 69220152D1
Authority
DE
Germany
Prior art keywords
primary input
analog logic
evaluation value
logic values
sequential circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220152T
Other languages
English (en)
Other versions
DE69220152T2 (de
Inventor
Hidetsugu Maekawa
Yasuharu Shimeki
Kazuhiro Kayashima
Hisao Niwa
Seiichi Shin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69220152D1 publication Critical patent/DE69220152D1/de
Application granted granted Critical
Publication of DE69220152T2 publication Critical patent/DE69220152T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69220152T 1991-08-30 1992-08-29 Prüfmustererzeugungsgerät Expired - Fee Related DE69220152T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP21989091 1991-08-30
JP28591891 1991-10-31
JP1177692 1992-01-27

Publications (2)

Publication Number Publication Date
DE69220152D1 true DE69220152D1 (de) 1997-07-10
DE69220152T2 DE69220152T2 (de) 1997-10-16

Family

ID=27279571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220152T Expired - Fee Related DE69220152T2 (de) 1991-08-30 1992-08-29 Prüfmustererzeugungsgerät

Country Status (4)

Country Link
US (1) US5434869A (de)
EP (1) EP0529670B1 (de)
JP (1) JPH05273310A (de)
DE (1) DE69220152T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0574919A3 (de) * 1992-06-18 1998-01-21 Matsushita Electric Industrial Co., Ltd. Zustandübergangdiagrammsgenerator und Prüfmustergenerator
JP2778547B2 (ja) * 1995-08-25 1998-07-23 松下電器産業株式会社 デジタル信号処理回路シミュレーション装置
US5771243A (en) * 1997-02-07 1998-06-23 Etron Technology, Inc. Method of identifying redundant test patterns
US5963888A (en) * 1997-10-22 1999-10-05 Uhlmann; Jeffrey K. Fast method and apparatus for nonlinearly transforming mean and covariance estimates
US8769361B2 (en) * 2003-10-07 2014-07-01 Advantest (Singapore) Pte Ltd Cost estimation for device testing
US11259115B2 (en) 2017-10-27 2022-02-22 VisiSonics Corporation Systems and methods for analyzing multichannel wave inputs

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317200A (en) * 1978-10-20 1982-02-23 Vlsi Technology Research Association Method and device for testing a sequential circuit divided into a plurality of partitions
US4754215A (en) * 1985-11-06 1988-06-28 Nec Corporation Self-diagnosable integrated circuit device capable of testing sequential circuit elements
EP0342787A3 (de) * 1988-04-15 1991-03-27 AT&T Corp. Suchverfahren zur Prüfvektorerzeugung für sequentielle Logikschaltungen
JPH03134579A (ja) * 1989-10-20 1991-06-07 Hitachi Ltd 多値計算モデルおよびそれを用いた論理回路のテストパターン生成方法
EP0574919A3 (de) * 1992-06-18 1998-01-21 Matsushita Electric Industrial Co., Ltd. Zustandübergangdiagrammsgenerator und Prüfmustergenerator

Also Published As

Publication number Publication date
JPH05273310A (ja) 1993-10-22
EP0529670A3 (en) 1993-12-15
EP0529670A2 (de) 1993-03-03
EP0529670B1 (de) 1997-06-04
US5434869A (en) 1995-07-18
DE69220152T2 (de) 1997-10-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee